Altera DDR Timing Wizard Manuel d'utilisateur télécharger pdf (Page 81)

Altera Corporation 3–21

November 2007 DDR Timing Wizard User Guide

Using the dtw_timing_analysis.tcl Script

Figure 3–10. Modified Project Settings Window

Decide When to Change Clock Phase Shift

This is applicable to DDR2/DDR SDRAM and RLDRAM II interfaces. In

RLDRAM II interfaces, this only applies for the address/command clock

setting.

When looking at the dtw_timing_analysis.tcl script results, pay attention

to the clocks used. Table 3–3 on page 3–10

has the default clock usage for

the memory controller’s dedicated clocks in 2-PLL mode. However, the

resynchronization or postamble clock may be shared with system clock or

write clock in a 1-PLL mode memory interface. In addition, the

address/command clock typically uses the inverted version of the system

clock.

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Altera DDR Timing Wizard Manuel d'utilisateur Page 81