Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 97
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Table 5-9: CPRI v6.0 IP Core RX_SCR Register at Offset 0x18
Bits Field Name Type Value on
Reset
Description
31 rx_scr_
active
RO 1'b0 Indicates that the incoming hyperframe is scrambled. The value
1 indicates that the incoming communication is scrambled, and
the value 0 indicates that it is not scrambled. The IP core
determines whether or not the incoming communication is
scrambled based on the protocol version.
30:0 rx_scr_
seed
RO 31'b0 Received scrambler seed. The receiver descrambles the
incoming CPRI communication based on this seed.
CM_CONFIG Register
Table 5-10: CPRI v6.0 IP Core CM_CONFIG Register at Offset 0x1C
Bits Field Name Type Value on
Reset
Description
31:13 Reserved UR0 19'b0
12
slow_cm_
rate_auto
RW 1'b1 Enable auto-negotiation of HDLC rate.
If you turn on Enable L1 inband protocol negotiator, this field
is a RW register field with the default value of 1. Otherwise, this
field is a RO register field with the default value of 0.
RO 1'b0
11 slow_cm_
rate_
filter
RW 1'b1 Enable filtering of HDLC rate.
10:8 tx_slow_
cm_rate
RW 3'b110 Rate configuration for slow Control and Management (HDLC).
To be inserted in CPRI control byte Z.66.0.
7
fast_cm_
ptr_auto
RW 1'b1 Enable auto-negotiation of Ethernet rate.
If you turn on Enable L1 inband protocol negotiator, this field
is a RW register field with the default value of 1. Otherwise, this
field is a RO register field with the default value of 0.
RO 1'b0
6 fast_cm_
ptr_
filter
RW 1'b1 Enable filtering of Ethernet rate.
5:0 tx_fast_
cm_ptr
RW 6'd20 Pointer to first CPRI control word used for fast Control and
Management (Ethernet). To be inserted in CPRI control byte Z.
194.0.
5-8
CM_CONFIG Register
UG-01156
2015.02.16
Altera Corporation
CPRI v6.0 IP Core Registers
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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