Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 77
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- Table des matières
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Noté. / 5. Basé sur avis des utilisateurs
The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an Avalon
master to this bus to access the registers of the embedded Arria 10 Native PHY IP core.
Table 3-25: CPRI v6.0 IP Core Arria 10 Transceiver Reconfiguration Interface Signals
The reconfig_clk clocks the signals on the CPRI v6.0 IP core Arria 10 transceiver reconfiguration interface.
Signal Name Direction Description
reconfig_clk Input Clocks the signals on the CPRI v6.0 transceiver reconfigura‐
tion interface. Supports frequency range 100–150 MHz.
reconfig_reset Input Asynchronous active-high reset signal. Resets the CPRI v6.0
Arria 10 transceiver reconfiguration interface and all of the
registers to which it provides access.
reconfig_write
Input You must assert this signal to request a write transfer.
reconfig_read
Input You must assert this signal to request a read transfer.
reconfig_address[9:0]
Input Address for reads and writes.
reconfig_
writedata[31:0]
Input Write data.
reconfig_
readdata[31:0]
Output Read data.
reconfig_waitrequest
Output The interface is busy. Do not issue Avalon-MM commands
to this interface while this signal is high.
Related Information
Avalon Interface Specifications
For more information about the Avalon-MM protocol, including timing diagrams, refer to the Avalon
Memory-Mapped Interfaces chapter.
Arria 10 Transceiver PHY User Guide
Information about the Arria 10 Native PHY IP core hard PCS registers that you can program through the
Arria 10 transceiver reconfiguration interface.
Arria 10 Transceiver Registers
Detailed information about the Arria 10 transceiver registers.
Interface to the External Reset Controller
Table 3-26: CPRI v6.0 IP Core External Reset Controller Interface Signals
The CPRI v6.0 IP core requires that you generate and connect at least one external transceiver reset controller.
Signal Name Direction Description
xcvr_tx_analogreset
Input Analog reset to transmitter from external reset controller.
xcvr_tx_digitalreset
Input Digital reset to transmitter from external reset controller.
UG-01156
2014.08.18
Interface to the External Reset Controller
3-47
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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