Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 68
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Specifying the Position in the Control Word
You can access only 32 bits in a single register access. Depending on the CPRI line bit rate, a control word
may have multiple 32-bit sections. Therefore, in addition to specifying the control word location in the
CPRI frame, you must also specify a 32-bit aligned position in the control word.
Table 3-13: Control Word Byte Positions in RX_CTRL and TX_CTRL Registers
In this table, each control word nibble is indicated with 0xF. The presence of 0xF or 0x0 indicates whether the
nibble within the register is populated with a valid control word nibble.
CPRI Bit Rate (Gbps)
Register Access Sequence Number ({rx,tx}_ctrl_seq)
0
(first access)
1
(2nd access)
2
(3rd access)
3
4th access)
4
(5th access)
0.6144 FF000000 0 0 0 0
1.2288 FFFF0000 0 0 0 0
2.4576 FFFFFFFF 0 0 0 0
3.072 FFFFFFFF FF000000 0 0 0
4.9152 FFFFFFFF FFFFFFFF 0 0 0
6.144 FFFFFFFF FFFFFFFF FFFF0000 0 0
9.8034 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0
10.1376 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FF000000
However, the table does not clarify which control word byte occupies which position in the register. The
following examples indicate the correspondence between register bytes and control word bytes:
• At the CPRI line bit rate of 0.6144 Gbps, when you access hyperframe control word X, the 8-bit control
word from hyperframe position #Z.X.0 is in bits [31:24] of the register.
• At the CPRI line bit rate of 1.2288 Gbps, the byte from position #Z.X.0.0 is in bits [31:24] of the
register and the byte from position #Z.X.0.1 is in bits [23:16] of the register.
• At the CPRI line bit rate of 3.072 Gbps, you must access the register twice to retrieve or write the full
control word. In the first access operation, you access the 32 bits of the control word in positions #Z.X.
0.0 (in register bits [31:24]), #Z.X.0.1 (in register bits [23:16]), #Z.X.0.2 (in register bits [15:8]), and
#Z.X.0.3 (in register bits [7:0]). In the second access operation, you access the eight bits of the control
word in position #Z.X.0.4 in bits [31:24] of the register.
Retrieving the Hyperframe Control Words
A control receive table contains one entry for each of the 256 control words in the current hyperframe. To
read a control word, your application must write the control word number X to the rx_ctrl_x field of the
CTRL_INDEX register and then read the last received #Z.X control word from the RX_CTRL register. Because
the register can hold only 32 bits at a time, depending on the CPRI line bit rate, reading the full control
word may require multiple register accesses. Increment the value in the rx_ctrl_seq field of the
CTRL_INDEX register from zero to four to access the full control word when the CPRI line bit rate is
10.1376 Gbps, or from zero to two when the CPRi line bit rate is 6.144 Gbps, for example.
3-38
Specifying the Position in the Control Word
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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