Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 74
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Table 3-18: Delays on Transmit Path Through CPRI v6.0 IP Core in Arria 10 Devices
In this table, P1 is the duration of one cpri_clkout clock cycle, and P2 is the duration of one TX PCS clock cycle.
tx_ex_delay is the value in the tx_ex_delay field of the TX_EX_DELAY register at offset 0x50. B2 is the number
of bits in a TX PCS clock cycle.
CPRI Line Bit Rate
(Gbps)
Bits per
cpri_clkout
Cycle
Bits per TX
PCS Clock
Cycle (=B2)
From AUX
TX Interface
to TX Buffer
Through TX
Buffer
Through
PCS
Through PMA
0.6144 32 10 (5 x P1) +
P2
tx_ex_delay 5 x P2 (3 x P2) + (2 x P2/
B2)
1.2288–9.8304 32 40 6 x P1 tx_ex_delay 4 x P2 32 x P2/B2
10.1376 32 40 (7 x P1) +
P2
tx_ex_delay
x 2
9 x P2 32 x P2/B2
Table 3-19: Delays on Receive Path Through CPRI v6.0 IP Core in Arria 10 Devices
In this table, P1 is the duration of one cpri_clkout clock cycle, and P2 is the duration of one RX PCS clock cycle.
rx_ex_delay is the value in the rx_ex_delay field of the RX_EX_DELAY register at offset 0x54.
CPRI Line Bit Rate
(Gbps)
Bits per
cpri_clkout
Cycle
Bits per RX
PCS Clock
Cycle (=B2)
Through
PMA
Through
PCS
Through RX
Buffer
From RX Buffer to AUX
RX Interface
0.6144 32 10 (2 x P2) +
(6 x P2/B2)
6 x P2 rx_ex_delay (7 x P1) + P2
1.2288–9.8304 32 40 31 x P2/B2 9 x P2 rx_ex_delay 8 x P1
10.1376 32 40 31 x P2/B2 5 x P2 rx_ex_delay
x 2
(7 x P1) + P2
Table 3-20: Delays on Transmit Path Through CPRI v6.0 IP Core in Stratix V Devices
In this table, P1 is the duration of one cpri_clkout clock cycle, and P2 is the duration of one TX PCS clock cycle.
tx_ex_delay is the value in the tx_ex_delay field of the TX_EX_DELAY register at offset 0x50.
CPRI Line Bit Rate
(Gbps)
Bits per
cpri_clkout
Cycle
Bits per TX
PCS Clock
Cycle (=B2)
From AUX
TX Interface
to TX Buffer
Through TX
Buffer
Through
PCS
Through PMA
0.6144 32 10 (5 x P1) +
P2
tx_ex_delay 3 x P2 (5 x P2) + (2 x P2/
B2)
1.2288–9.8304 32 40 6 x P1 tx_ex_delay 2 x P2 (2 x P2) + (3 x P2/
B2)
10.1376 32 40 (7 x P1) +
P2
tx_ex_delay
x 2
6 x P2 (2 x P2) + (3 x P2/
B2)
3-44
Deterministic Latency
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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