Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 71
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Table 3-14: Auto-Rate Negotiation Control and Status Interface Signals
All interface signals are clocked by the cpri_clkout clock.
Signal Name Direction Description
nego_bitrate_in[4:0] Input CPRI line bit rate to be used in next attempt to achieve
frame synchronization, encoded according to the
following valid values:
• 5'b00001: 0.6144 Gbps
• 5'b00010: 1.2288 Gbps
• 5'b00100: 2.4576 Gbps
• 5'b00101: 3.0720 Gbps
• 5'b01000: 4.9150 Gbps
• 5'b01010: 6.1440 Gbps
• 5'b10000: 9.8304 Gbps
• 5'b10100: 10.1376 Gbps
This signal has higher priority than the bit_rate field in
the BIT_RATE_CONFIG register at offset 0x0C. When this
signal has the value of 5'b00000, the CPRI v6.0 IP core
responds to the register field.
nego_bitrate_out[4:0]
Output Reflects the current actual CPRI line bit rate.
Related Information
BIT_RATE_CONFIG Register on page 5-5
Extended Delay Measurement
The CPRI v6.0 IP core uses a dedicated clock, ex_delay_clk, to measure the delay through the RX and
TX internal buffers to your desired precision. The extended delay process is identical for the two
directions of flow through the IP core; the TX_EX_DELAY and RX_EX_DELAY registers hold the same
information for the two directions.
The tx_msrm_period field of the TX_EX_DELAY register contains the value N, such that N clock periods of
the ex_delay_clk clock are equal to some whole number M of cpri_clkout periods. For example, N
may be a multiple of M, or the M/N frequency ratio may be slightly greater than 1, such as 64/63 or
128/127. The application layer specifies N to ensure the accuracy your application requires. The accuracy
of the Tx buffer delay measurement is N/least_common_multiple(N,M) cpri_clkout periods.
Similarly, the rx_msrm_period field of the RX_EX_DELAY register contains the value N, such that N clock
periods of the ex_delay_clk clock are equal to some whole number M of cpri_clkout periods.
If your application does not require this precision, drive the ex_delay_clk input port with the
cpri_clkout signal. In this case, the M/N ratio of 1 because the frequencies are the same.
The tx_buf_delay field of the TX_DELAY register indicates the number of 32-bit words currently in the Tx
buffer. After you program the tx_msrm_period field of the TX_EX_DELAY register with the value of N, the
tx_ex_delay field of the TX_EX_DELAY register holds the current measured delay through the Tx buffer.
The unit of measurement is cpri_clkout periods. The tx_ex_delay_valid field indicates that a new
measurement has been written to the tx_ex_delay field since the previous register read. The following
UG-01156
2014.08.18
Extended Delay Measurement
3-41
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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