Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 32
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Multiple interfaces control the contents of the outbound CPRI frame control words and data. The CPRI
v6.0 implements the following transmission priorities among these interfaces:
• CPRI frame control words:
1. If the IP core implements the AUX interface, the AUX interface aux_tx_data bus, with appropriate
delay, has first priority in filling in the outbound CPRI frame control words.
2. If the IP core does not implement the AUX interface, or the aux_tx_mask value associated with the
relevant incoming data blocks the relevant aux_tx_data bits, each of the following interfaces, if
implemented, has secondary priority in filling the relevant part of the outbound CPRI frame
control words:
• Real-time vendor specific interface (RTVS)
• Vendor specific interface (VS)
• AxC control information interface (Ctrl_AxC)
3. For any part of the CPRI frame control words not filled in by one of the previous methods, the
transmission-enabled values most recently written to the control transmit table through the full
control word access registers CTRL_INDEX and TX_CTRL determine the contents of the outbound
CPRI frame control words. If the most recently written word for a CPRI frame position is not
transmission-enabled, no transmission is authorized from the control transmit table to that CPRI
frame position.
4. If none of the previous methods provides the content for a position in the CPRI frame control
word, the following interfaces, if implemented have the lowest priority in filling the relevant part of
the outbound CPRI frame control words:
• Fast control and management (Ethernet) MII interface
• Slow control and management (HDLC) serial interface
• L1 control and status interface
• Dedicated registers that contain or control content for control word positions in the CPRI
frame. For example, the rx_prot_ver_filter field of the PROT_VER register
• Transmission of special symbols according to the CPRI protocol. For example, K28.5, D16.2, /S/,
or /T/
• CPRI frame I/Q data words:
1. If the IP core implements the AUX interface, the AUX interface aux_tx_data bus, with appropriate
delay, has first priority in filling in the outbound CPRI frame I/Q data words.
2. If the IP core does not implement the AUX interface, or the aux_tx_mask value associated with the
relevant incoming data blocks the relevant aux_tx_data bits, the Direct I/Q interface, if
implemented, has secondary priority in filling the relevant part of the outbound CPRI frame I/Q
data words.
3-2
Interfaces Overview
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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