Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 80
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Table 3-29: Loopback Modes
Tag in Figure Description How to Configure
1 External loopback: Use this configuration
to test the full Tx and Rx paths from an
application through the CPRI link and
back to the application.
Connect a CPRI REC master's CPRI Tx interface
to its CPRI Rx interface by physically connecting
the CPRI v6.0 IP core's high-speed transceiver
output pins to its high-speed transceiver input
pins.
The connection medium must support the data
rate requirements of the CPRI v6.0 IP core.
2 Transceiver PMA serial forward loopback
path is active.
Turn on Enable transceiver PMA forward
loopback path (Tx to Rx) in the parameter editor
and set the loop_forward field of the LOOPBACK
register to the value 2'b01.
3 Active parallel loopback path does not
exercise the transceiver.
Turn on Enable forward loopback path (Tx to
Rx) in the parameter editor and set the loop_
forward field of the LOOPBACK register to the value
2'b10 (to include the stitching logic to the
transceiver) or 2'b11 (to exclude the stitching
logic to the transceiver).
4 Reverse loopback path is active. Turn on Enable reversed loopback path (Rx to
Tx) in the parameter editor and set the loop_
reversed field of the LOOPBACK register to a non-
zero value. The register value specifies the parts of
the CPRI frame that participate in the loopback
path. Other parts of the CPRI frame are filled in
from the local IP core.
Related Information
LOOPBACK Register on page 5-14
CPRI v6.0 IP Core Self-Synchronization Feature
Altera provides a self-synchronization testing feature that supports an RE slave in a CPRI link external
loopback configuration. This feature is intended to work correctly only for Layer 1 testing.
By default, only an REC master can function correctly in a CPRI link external loopback configuration. An
RE slave in external loopback configuration cannot achieve frame synchronization, because the CPRI RX
interface must lock on to the K28.5 character before the CPRI TX interface can begin sending K28.5
characters. Therefore, no K28.5 character is ever transmitted on the RE slave loopback CPRI link.
However, in an Altera RE slave CPRI v6.0 IP core you can specify that the CPRI TX interface begin
sending K28.5 characters before the CPRI Rx interface locks on to the K28.5 character from the CPRI link.
This feature supports a CPRI RE slave in achieving frame synchronization without being connected to a
CPRI master, and allows you to test your CPRI RE slave without the need for an additional CPRI v6.0 IP
core.
To turn on this feature, connect your CPRI RE slave in a CPRI link external loopback configuration, and
set the tx_enable_force field of the L1_CONFIG register to the value of 1.
3-50
CPRI v6.0 IP Core Self-Synchronization Feature
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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