Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 49
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various direct interfaces in this format. The only exception is the L1 CSR interface, which transmits and
receives information in individual bits.
Figure 3-12: AUX Interface Data at Different CPRI Line Bit Rates
The AUX interface presents and expects data in fixed 32-bit words. The mapping of the CPRI frame to
and from 32-bit words depends on the CPRI v6.0 IP core bit rate. This figure illustrates how CPRI frame
words are mapped to 32-bit words on the AUX interface 32-bit data bus.
0.6144 Gbps
Line Rate:
1.2288 Gbps
Line Rate:
2.4576 Gbps
Line Rate:
3.072 Gbps
Line Rate:
0 1 2 3
[31:24]
#Z.X.0.0
(1)
#Z.X.4.0 #Z.X.8.0 #Z.X.12.0
[23:16] #Z.X.1.0 #Z.X.5.0 #Z.X.9.0 #Z.X.13.0
[15:8] #Z.X.2.0 #Z.X.6.0 #Z.X.10.0 #Z.X.14.0
[7:0] #Z.X.3.0 #Z.X.7.0 #Z.X.11.0 #Z.X.15.0
0 1 2 ... 7
[31:24]
#Z.X. 0.0
(1)
#Z.X.2.0 #Z.X.4.0 ... #Z.X.14.0
[23:16]
#Z.X. 0.1
(1)
#Z.X.2.1 #Z.X.4.1 ... #Z.X.14.1
[15:8] #Z.X.1.0 #Z.X.3.0 #Z.X.5.0 ... #Z.X.15.0
[7:0] #Z.X.1.1 #Z.X.3.1 #Z.X.5.1 ... #Z.X.15.1
0 1 2 ... 15
[31:24]
#Z.X.0.0
(1)
#Z.X.1.0 #Z.X.2.0 ... #Z.X.15.0
[23:16] #Z.X.0.1
(1)
#Z.X.1.1 #Z.X.2.1 ... #Z.X.15.1
[15:8] #Z.X.0.2
(1)
#Z.X.1.2 #Z.X.2.2 ... #Z.X.15.2
[7:0] #Z.X.0.3
(1)
#Z.X.1.3 #Z.X.2.3 ... #Z.X.15.3
0 1 2 ... 18 19
[31:24] #Z.X.0.0
(1)
#Z.X.0.4
(1)
#Z.X.1.3 ... #Z.X.14.2 #Z.X.15.1
[23:16] #Z.X.0.1
(1)
#Z.X.1.0 #Z.X.1.4 ... #Z.X.14.3 #Z.X.15.2
[15:8] #Z.X.0.2
(1)
#Z.X.1.1 #Z.X.2.0 ... #Z.X.14.4 #Z.X.15.3
[7:0] #Z.X.0.3
(1)
#Z.X.1.2 #Z.X.2.1 ... #Z.X.15.0 #Z.X.15.4
Sequence number on AUX interface
Sequence number on AUX interface
Sequence number on AUX interface
Sequence number on AUX interface
UG-01156
2014.08.18
Direct Interface CPRI Frame Data Format
3-19
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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