Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 67
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Accessing the Hyperframe Control Words
When you turn on Enable all control word access in the CPRI v6.0 parameter editor, you can access the
256 control words in a hyperframe through the CPRI v6.0 IP core CPU interface. The CTRL_INDEX register
and the RX_CTRL register support your application in reading the incoming control words, and the
L1_CONFIG register, CTRL_INDEX register, and TX_CTRL register support the application in writing to
outgoing control words.
Register support provides you access to the full control word. Alternatively, in timing-critical applications,
you can access the full control words through the CPRI v6.0 IP core AUX interface or other dedicated
direct interfaces.
Note:
Altera recommends that you use the CPU interface to access the hyperframe control words only in
applications that are not timing-critical.
Specifying the Control Word
Figure 3-27: Subchannels in a Hyperframe
Illustrates how the 256 control words in the hyperframe are organized as 64 subchannels of four control
words each. The figure illustratres why the index X of a control word is Ns + 64 + Xs, where Ns is the
subchannel index and Xs is the index of the control word within the subchannel.
Xs == 0123
Ns == 0 0: K28.5 Synchronization and Timing
1 1: HDLC link 65: HDLC 129: HDLC 193: HDLC
2 2: L1 In-band 66: L1 in-band 130: L1 in-band 194: P (20 = 0x14)
3 3: Reserved 67: Reserved
4 4: Ctrl_AxC ... ... ...
...
7 7: Ctrl_AxC 71: Ctrl_AxC 135: Ctrl_AxC 199: Ctrl_AxC
...
14 14: Reserved
15 15: Reserved 79: Reserved 143: Reserved 207: Reserved
16 Vendor-specific
...
19
20
Pointer P --->
20: Ethernet
...
62
62 126 190 254
63
63 127 191 255
The rx_ctrl_x and tx_ctrl_x fields of the CTRL_INDEX register hold the X value of the control word you
want to access through the control and status interface.
UG-01156
2014.08.18
Accessing the Hyperframe Control Words
3-37
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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