Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 85

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Signal Name Direction Description
hdlc_rx_valid Output Direct HDLC serial RX interface
These signals are available only if you turn on Enable
direct HDLC serial interface in the CPRI v6.0 parameter
editor.
hdlc_rx_data Output
hdlc_tx_ready Output Direct HDLC serial TX interface
These signals are available only if you turn on Enable
direct HDLC serial interface in the CPRI v6.0 parameter
editor.
hdlc_tx_valid Input
hdlc_tx_data Input
z130_local_lof Output
Direct L1 control and status interface
These signals are available only if you turn on Enable Z.
130.0 access interface in the CPRI v6.0 parameter editor.
z130_local_los Output
z130_sdi_assert Input
z130_local_rai Output
z130_reset_assert Input
z130_remote_lof Output
z130_remote_los Output
z130_sdi_req Output
z130_remote_rai Output
z130_reset_req Output
Related Information
AUX Interface on page 3-9
AUX Interface Signals on page 3-10
Direct IQ Interface on page 3-21
Direct Ctrl_AxC Control Words Interface
Direct Vendor Specific Access Interface on page 3-23
Real-Time Vendor Specific Interface on page 3-25
Direct HDLC Serial Interface on page 3-27
Direct L1 Control and Status Interface on page 3-29
CPRI v6.0 IP Core Management Interfaces
The CPRI v6.0 IP core provides multiple interfaces for managing the IP core and the properties of the
CPRI link.
4-4
CPRI v6.0 IP Core Management Interfaces
UG-01156
2014.08.18
Altera Corporation
CPRI v6.0 IP Core Signals
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