Altera CPRI v6.0 MegaCore Function Manuel d'utilisateur Page 51
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Direct IQ Interface
If you turn on Enable direct IQ mapping interface in the CPRI v6.0 parameter editor, the direct IQ
interface is available. This interface allows direct access to the I/Q data time slots in the CPRI frame. You
can connect this interface to any user-defined air standard I/Q mapping module.
This interface is Avalon-ST compliant with a read latency value of 1.
You can alter the transmit latency with the Auxiliary latency cycle(s) parameter.
Table 3-6: Direct IQ Interface Signals
All interface signals are clocked by the cpri_clkout clock.
Direct IQ RX Interface
Signal Name Direction Description
iq_rx_valid[3:0] Output Each asserted bit indicates the corresponding byte on the
current iq_rx_data bus is valid I/Q data.
iq_rx_data[31:0] Output I/Q data received from the CPRI frame. The iq_rx_valid
signal indicates which bytes are valid I/Q data bytes.
Direct IQ TX Interface
Signal Name Direction Description
iq_tx_ready[3:0] Output Each asserted bit indicates the IP core is ready to read I/Q
data from the corresponding byte of iq_tx_data on the
next clock cycle.
iq_tx_valid[3:0] Input Write valid for iq_tx_data. Assert bit [n] to indicate that
the corresponding byte on the current iq_tx_data bus is
valid I/Q data.
iq_tx_data[31:0] Input I/Q data to be written to the CPRI frame. The IP core
writes the individual bytes of the current value on the iq_
tx_data bus to the CPRI frame based on the iq_tx_ready
signal from the previous cycle, and the iq_tx_valid
signal in the current cycle.
UG-01156
2014.08.18
Direct IQ Interface
3-21
Functional Description
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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