Altera Stratix GX Transceiver Manuel d'utilisateur Page 131
- Page / 318
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Altera Corporation 5–19
January 2005 Stratix GX Transceiver User Guide
XAUI Mode
receive a clock supply. In this case, there must be no frequency difference
between the tx_coreclk and the transmitter PLL clock. The transmitter
Phase Compensation FIFO module can only account for phase
differences.
If the tx_coreclk is not selected as an optional input transmitter port,
tx_coreclk is fed by coreclk_out. This connection occurs using the
logic array routing. As such, the software defaults to using an FPGA
global clock, regional clock, or fast regional clock resource.
The transmitter phase compensation FIFO module is always used and
cannot be bypassed. The input to this FIFO module is the data from the
FPGA logic array. If they are used, the tx_ctrlenable and
tx_forcedisparity signals are also passed through the FIFO module
to ensure that they are synchronized with the data when they feed to the
subsequent module.
Byte Serializer
The byte serializer in the transmitter block takes a 16-bit input from the
FPGA logic array and serializes it to 8 bits. It transmits from the least
significant byte to the most significant byte. The transmitter digital reset
must always be used to reset the FIFO module pointers whenever an
unknown state is encountered, such as when the transmitter PLL loses
lock. Refer to the chapter Reset Control & Power Down for further details
on the reset sequence.
Figure 5–16 demonstrates input and output signals of the byte serializer
when serializing a 20-bit input to 10 bits. The tx_in[] signal is the input
that has already passed from the FPGA logic array through the
transmitter phase compensation FIFO module.
Figure 5–16. Transmitter Byte Serializer in 16- to 8-Bit Mode
The LSB is transmitted before the MSB in the transmitter byte serializer.
Figure 5–16 shows the order of data transmitted. For the input of D1, the
output is D1LSB and then D1MSB.
xxxxxxxx
xxxxxxxx 01101111
0001010001101111
datain[15:0]
dataout[7:0]
1100011011110001
1010101010110011
00010100 11110001 11000110
D1 D2 D3
D1
LSB
D1
MSB
D2
LSB
D2
MSB
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- (408) 544-7000 1
- Contents 3
- Chapter 4. SONET Mode 4
- Chapter 5. XAUI Mode 4
- Chapter 6. GigE Mode 5
- Chapter 7. Loopback Modes 5
- About This User Guide 7
- Typographic 8
- Conventions 8
- 1. Introduction 9
- Transceiver 10
- Architecture 10
- Digital Overview 11
- Byte Serializer/Deserializer 12
- 8B/10B Encoder/Decoder 12
- Modes of 13
- Operation 13
- Loopback 17
- Built-In Self Test 17
- 1–10 Altera Corporation 18
- Modes of Operation 18
- 2. Stratix GX Analog 19
- Description 19
- Programmable Pre-Emphasis 22
- Transmitter PLL 23
- Clock Synthesis 24
- 2–8 Altera Corporation 26
- Transmitter Analog 26
- Receiver Analog 27
- 2–10 Altera Corporation 28
- Equalizer Mode 29
- Receiver PLL 30
- 2–14 Altera Corporation 32
- Receiver Bandwidth Type 33
- Clock Recovery Unit 34
- Altera Corporation 2–17 35
- Stratix GX Analog Description 35
- 2–18 Altera Corporation 36
- Altera Corporation 2–19 37
- Analog Features 38
- Notes (1)–(4) 39
- 2–22 Altera Corporation 40
- MegaWizard Analog Features 40
- Notes to Figure 2–14: 40
- Altera Corporation 2–23 41
- Note to Figure 2–15: 41
- 2–24 Altera Corporation 42
- Notes to Figure 2–16: 42
- Altera Corporation 2–25 43
- Notes to Figure 2–17: 43
- 2–26 Altera Corporation 44
- Notes to Figure 2–18: 44
- Altera Corporation 2–27 45
- 2–28 Altera Corporation 46
- 3. Basic Mode 47
- Basic Mode 48
- Manual Alignment Modes 51
- 3–6 Altera Corporation 52
- Altera Corporation 3–7 53
- 3–8 Altera Corporation 54
- 3–14 Altera Corporation 60
- Altera Corporation 3–15 61
- Byte Serializer 63
- Altera Corporation 3–21 67
- 3–22 Altera Corporation 68
- Basic Mode Clocking 68
- TX_PLL_CLK. If not available 70
- CORECLK_OUT through logic 70
- RX_CLKOUT 70
- Altera Corporation 3–25 71
- Altera Corporation 3–27 73
- 3–28 Altera Corporation 74
- 3–30 Altera Corporation 76
- Basic Mode MegaWizard Plug-In 76
- Notes to Figure 3–25: 76
- Altera Corporation 3–31 77
- Notes to Figure 3–26: 77
- 3–32 Altera Corporation 78
- Notes to Figure 3–27: 78
- Altera Corporation 3–33 79
- Notes to Figure 3–28: 79
- 3–34 Altera Corporation 80
- Notes to Figure 3–29: 80
- Altera Corporation 3–35 81
- Notes to Figure 3–30: 81
- 3–36 Altera Corporation 82
- 4. SONET Mode 83
- Altera Corporation 4–5 87
- 4–6 Altera Corporation 88
- Altera Corporation 4–7 89
- Altera Corporation 4–9 91
- 4–10 Altera Corporation 92
- Altera Corporation 4–13 95
- 4–14 Altera Corporation 96
- Altera Corporation 4–15 97
- TX_PLL_CLK. Available 98
- 4–18 Altera Corporation 100
- SONET Mode Clocking 100
- Altera Corporation 4–19 101
- SONET Mode 101
- Altera Corporation 4–21 103
- 4–22 Altera Corporation 104
- MegaWizard 105
- Plug-In Manager 105
- 4–24 Altera Corporation 106
- Notes to Figure 4–17: 106
- Altera Corporation 4–25 107
- Notes to Figure 4–18: 107
- 4–26 Altera Corporation 108
- Notes to Figure 4–19: 108
- Altera Corporation 4–27 109
- Notes to Figure 4–20: 109
- 4–28 Altera Corporation 110
- Notes to Figure 4–21: 110
- Altera Corporation 4–29 111
- Notes to Figure 4–22: 111
- 4–30 Altera Corporation 112
- 5. XAUI Mode 113
- 5–2 Altera Corporation 114
- Introduction 114
- XAUI Mode 117
- Receiver 117
- Word Aligner 118
- XAUI Synchronization Mode 119
- 5–8 Altera Corporation 120
- Note to Figure 5–6: 120
- Channel Aligner 121
- 5–10 Altera Corporation 122
- Rate Matcher 123
- 8B/10B Decoder 123
- 10-Bit Decoding 124
- Code Error Detect 124
- Disparity Error Detector 125
- Control Detect 126
- PCS - XGMII Code Conversion 127
- Byte Deserializer 127
- 5–16 Altera Corporation 128
- Altera Corporation 5–17 129
- Transmitter 130
- Altera Corporation 5–19 131
- 5–20 Altera Corporation 132
- 8B/10B Encoder 133
- 8B/10B Reset Condition 134
- Control Code Encoding 135
- Clocking 136
- Altera Corporation 5–25 137
- 5–26 Altera Corporation 138
- XAUI Mode Clocking 138
- 5–28 Altera Corporation 140
- Altera Corporation 5–29 141
- 5–30 Altera Corporation 142
- 5–32 Altera Corporation 144
- Altera Corporation 5–33 145
- Altera Corporation 5–35 147
- Notes to Figure 5–28: 147
- 5–36 Altera Corporation 148
- Notes to Figure 5–29: 148
- Altera Corporation 5–37 149
- Notes to Figure 5–30: 149
- 5–38 Altera Corporation 150
- Notes to Figure 5–31: 150
- Altera Corporation 5–39 151
- Notes to Figure 5–32: 151
- 5–40 Altera Corporation 152
- Notes to Figure 5–33: 152
- Altera Corporation 5–41 153
- 5–42 Altera Corporation 154
- 6. GigE Mode 155
- /C1/ and /C2/ code groups 156
- /K28.5/D21.5/Config_Reg (1) 156
- GigE Mode 158
- Pattern Detector Module 159
- 6–6 Altera Corporation 160
- Altera Corporation 6–7 161
- 6–8 Altera Corporation 162
- 6–10 Altera Corporation 164
- /K28.5/, /D5.6/) and 170
- 6–18 Altera Corporation 172
- Altera Corporation 6–21 175
- 6–22 Altera Corporation 176
- GigE Mode Clocking 176
- Altera Corporation 6–23 177
- Clock Port Description 178
- 6–26 Altera Corporation 180
- 6–28 Altera Corporation 182
- Altera Corporation 6–29 183
- 6–30 Altera Corporation 184
- 6–32 Altera Corporation 186
- GigE Mode MegaWizard 186
- Notes to Figure 6–27: 186
- Altera Corporation 6–33 187
- Notes to Figure 6–28: 187
- 6–34 Altera Corporation 188
- Notes to Figure 6–29: 188
- Altera Corporation 6–35 189
- Notes to Figure 6–30: 189
- 6–36 Altera Corporation 190
- Notes to Figure 6–31: 190
- Altera Corporation 6–37 191
- Notes to Figure 6–32: 191
- Design Example 192
- Altera Corporation 6–39 193
- 6–40 Altera Corporation 194
- Altera Corporation 6–41 195
- 6–42 Altera Corporation 196
- Altera Corporation 6–43 197
- 6–44 Altera Corporation 198
- Altera Corporation 6–45 199
- 6–46 Altera Corporation 200
- 7. Loopback Modes 201
- Parallel 202
- Non-Active Path 203
- Active Path 203
- Altera Corporation 8–1 205
- January 2005 205
- Notes to Figure 8–1: 205
- PRBS Mode Generator 206
- Incremental Mode Generator 207
- High-Frequency Mode Generator 207
- Low-Frequency Mode Generator 208
- Pattern Verifier 209
- Incremental Mode Verifier 210
- Examples 211
- 8–8 Altera Corporation 212
- Design Examples 212
- Altera Corporation 8–9 213
- 8–10 Altera Corporation 214
- Altera Corporation 8–11 215
- 8–12 Altera Corporation 216
- Altera Corporation 8–13 217
- 8–14 Altera Corporation 218
- Altera Corporation 8–15 219
- 8–16 Altera Corporation 220
- Altera Corporation 8–17 221
- 8–18 Altera Corporation 222
- Altera Corporation 8–19 223
- 8–20 Altera Corporation 224
- Altera Corporation 8–21 225
- 8–22 Altera Corporation 226
- 9. Reset Control & 227
- Power Down 227
- 9–2 Altera Corporation 228
- 9–4 Altera Corporation 230
- Recommended Resets 230
- Altera Corporation 9–5 231
- 9–6 Altera Corporation 232
- 9–8 Altera Corporation 234
- Altera Corporation 9–9 235
- 9–10 Altera Corporation 236
- Altera Corporation 9–11 237
- Altera Corporation 9–13 239
- 9–14 Altera Corporation 240
- Altera Corporation 9–15 241
- 9–16 Altera Corporation 242
- Altera Corporation 9–17 243
- 9–18 Altera Corporation 244
- Altera Corporation 9–19 245
- 9–20 Altera Corporation 246
- Altera Corporation 9–21 247
- Altera Corporation 248
- Altera Corporation 9–23 249
- 9–24 Altera Corporation 250
- Altera Corporation 9–25 251
- 9–26 Altera Corporation 252
- 9–28 Altera Corporation 254
- Altera Corporation 9–29 255
- 9–30 Altera Corporation 256
- Altera Corporation 9–31 257
- Receiver Reset 258
- Altera Corporation 9–33 259
- Altera Corporation 9–35 261
- 9–36 Altera Corporation 262
- Altera Corporation 9–37 263
- 9–38 Altera Corporation 264
- 9–40 Altera Corporation 266
- Altera Corporation 9–41 267
- 9–42 Altera Corporation 268
- Altera Corporation 9–43 269
- 9–44 Altera Corporation 270
- 9–46 Altera Corporation 272
- Altera Corporation 9–47 273
- 9–48 Altera Corporation 274
- 9–50 Altera Corporation 276
- Altera Corporation 9–51 277
- Transmitter Reset 278
- Altera Corporation 9–53 279
- Stable TXPLL Clock 280
- Altera Corporation 9–55 281
- 9–56 Altera Corporation 282
- 8B/10B Code 285
- A–2 Altera Corporation 286
- Supported Codes 287
- A–12 Altera Corporation 296
- Appendix B. Ports & 297
- Parameters 297
- Output Ports 301
- Parameter 305
- Descriptions 305
- port must be used 309
- Appendix C. REFCLKB Pin 311
- Constraints 311
- C–2 Altera Corporation 312
- Known Issues 312
- Quartus II Software Messages 313
- Recommendations 315
- C–6 Altera Corporation 316
- Altera Corporation C–7 317
- C–8 Altera Corporation 318
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