Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manuel d'utilisateur télécharger pdf (Page 740)

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SystemVerilog AXI3 and AXI4 Test Programs

SystemVerilog AXI4 Slave BFM Test Program

September 2013

SystemVerilog AXI4 Slave BFM Test Program

The following code example contains a simple AXI4 slave test program that shows the slave

BFM API being used to communicate with a master and create stimulus. This test program is

discussed further in the SystemVerilog Tutorials chapter.

// **********************************************************************

// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION

// WHICH IS THE PROPERTY OF

// MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE

// TERMS.

// **********************************************************************

This is a simple example of an AXI4 Slave to demonstrate the

mgc_axi4_slave BFM usage.

This is a fairly generic slave which handles almost all write and read

transaction

scenarios from master. It handles write data with address as well as

data after address

both.

This slave code is divided in two parts, one which user might need to

edit to change slave

mode (Transaction/burst or Phase level) and memory handling.

import mgc_axi4_pkg::*;

module slave_test_program #(int AXI4_ADDRESS_WIDTH = 32, int

AXI4_RDATA_WIDTH = 1024, int AXI4_WDATA_WIDTH = 1024, int AXI4_ID_WIDTH =

18, int AXI4_USER_WIDTH = 8, int AXI4_REGION_MAP_SIZE = 16)

(

mgc_axi4_slave bfm

);

typedef bit [((AXI4_ADDRESS_WIDTH) - 1) : 0] addr_t;

// Enum type for slave mode

// AXI4_TRANSACTION_SLAVE - Works at burst level(write data is received

// at burst and read data/response is sent in burst)

// AXI4_PHASE_SLAVE - Write data and read data/response is worked

upon

// at phase level

typedef enum bit

{

AXI4_TRANSACTION_SLAVE = 1'b0,

AXI4_PHASE_SLAVE = 1'b1

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Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manuel d'utilisateur Page 740

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