Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manuel d'utilisateur Page 186
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Mentor VIP AE AXI3/4 User Guide, V10.2b
168
SystemVerilog Tutorials
Verifying a Master DUT
September 2013
AXI4 BFM Slave Test Program
The Slave Test Program is a memory model that contains two APIs: a AXI4 Basic Slave API
Definition and an AXI4 Advanced Slave API Definition.
The AXI4 Basic Slave API Definition allows you to create a wide range of stimulus scenarios to
test a master DUT. This API definition simplifies the creation of slave stimulus based on the
default response of OKAY to master read and write transactions.
The AXI4 Advanced Slave API Definition allows you to create additional response scenarios to
transactions. For example, a successful exclusive transaction requires an EXOKAY response.
For a complete code listing of the slave test program, refer to “SystemVerilog AXI4 Slave BFM
Test Program” on page 720.
AXI4 Basic Slave API Definition
The Basic Slave Test Program API contains:
• Functions that read and write a byte of data to Internal Memory include do_byte_read()
and do_byte_write(), respectively.
• Functions set_read_data_valid_delay() and set_wr_resp_valid_delay() to configure the
delay of the read data channel RVALID, and write response channel BVALID signals,
respectively.
• Variables m_rd_addr_phase_ready_delay and m_wr_addr_phase_ready_delay to
configure the delay of the read/write address channel ARVALID/AWVALID signals, and
m_wr_data_phase_ready_delay to configure the delay of the write response channel
BVALID signal.
• A slave_mode variable to configure the behavior of reading and writing to the internal
memory.
• A slave_ready_delay_mode variable to configure the behavior of the handshake signals
*VALID to *READY delay.
• Configuration variables m_max_outstanding_read_trans and
m_max_outstanding_write_trans back-pressure a master from transmitting additional
read and write transactions when the configured value has been reached.
- Verification IP Altera 1
- Edition 1
- AMBA AXI3/4 1
- User Guide 1
- Table of Contents 10
- List of Examples 13
- List of Figures 16
- List of Tables 17
- About This User Guide 19
- Protocol Restrictions 19
- Supported Simulators 20
- Simulator GCC Requirements 21
- Chapter 1 23
- Mentor VIP Altera Edition 23
- What Is a Transaction? 24
- An AXI Transaction 24
- Chapter 2 31
- SystemVerilog API Overview 31
- Transaction Record 33
- Table 2-1. Transaction Fields 35
- AXI3 BFM Delay Mode 48
- Chapter 3 51
- SystemVerilog Master API 57
- Chapter 4 87
- SystemVerilog Slave API 93
- Operational 100
- Transaction 100
- AXI3 Example 101
- AXI4 Example 101
- September 2013 107
- AXI3 BFM 109
- Helper Functions 118
- Chapter 5 121
- Monitor BFM Protocol Support 122
- Monitor Timing and Events 122
- Monitor BFM Configuration 122
- Timing Variables 124
- Slave Attributes 125
- Error Detection 125
- Monitor Assertions 126
- SystemVerilog Monitor API 127
- Prototype 128
- Arguments 128
- Arguments config_name 130
- (AXI4) Configuration name: 130
- Chapter 6 155
- SystemVerilog Tutorials 155
- AXI3 BFM Master Test Program 156
- AXI4 BFM Master Test Program 161
- Verifying a Slave DUT 162
- Verifying a Master DUT 173
- Example 6-30. process_write 184
- Example 6-31. handle_write 185
- AXI4 BFM Slave Test Program 186
- Internal Memory 187
- Example 6-44. handle_read 197
- Example 6-45. process_write 198
- Chapter 7 203
- VHDL API Overview 203
- Test Program VHDL 204
- VHDL to SV Wrapper 204
- Configuration 205
- Creating Transactions 206
- AXI4 Transaction Definition 207
- Table 7-1. Transaction Fields 209
- Transaction Field Description 209
- Protocol Transaction Fields 209
- Executing Transactions 212
- Waiting Events 213
- Access Transaction Record 214
- Operation Mode 216
- Channel Handshake Delay 217
- AXI4 BFM Handshake Delay 218
- Data Beat Done 220
- Transaction Done 220
- Chapter 8 221
- Master BFM Protocol Support 222
- Master Timing and Events 222
- Master BFM Configuration 222
- Master Assertions 225
- AXI4 Assertion Configuration 226
- VHDL Master API 227
- Protocol 233
- Arguments cache 255
- AXI4 BFM 297
- Chapter 9 365
- VHDL AXI3 and AXI4 Slave BFMs 365
- Slave BFM Configuration 366
- Slave Assertions 369
- AXI3 Assertion Configuration 370
- VHDL Slave API 371
- Returns transaction_id 378
- Chapter 10 505
- VHDL Monitor API 511
- Chapter 11 627
- VHDL Tutorials 627
- Example 11-29. handle read 656
- Example 11-38. process_write 668
- Chapter 12 673
- Running the Qsys Tool 676
- Running Simulation 679
- Example Script Processing 682
- Appendix A 685
- Assertions 685
- AXI4 Assertions 698
- Appendix B 715
- Programs 715
- Appendix C 751
- End-User License Agreement 779
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