Altera Stratix III Development Board Manuel d'utilisateur Page 81
- Page / 82
- Table des matières
- MARQUE LIVRES
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- General Description 7
- Handling the Board 8
- 2. Board Components 9
- MSEL0 to GND 10
- Jumper (J13) 10
- Board Overview 11
- Featured FPGA (U22) 12
- Device Support 14
- I/O Resources 14
- MAX II CPLD 16
- FPGA Programming Over USB 25
- Notes to Table 2–7: 26
- Status Elements 27
- Board Specific LEDs 28
- Power Display 29
- JTAG Control DIP Switch 29
- Power Select Rotary Switch 31
- Clocking Circuitry 33
- Stratix III FPGA Clock Inputs 34
- General User Interfaces 36
- Note to Table 2–21: 37
- General User-Defined LEDs 38
- HSMC User-Defined LEDs 39
- User 7-Segment Display 40
- Power 7-Segment Display 41
- Character LCD 41
- Graphics LCD 43
- Radio at www.njr.co.jp 45
- Speaker Header 46
- Components and Interfaces 47
- High-Speed Mezzanine Cards 49
- On-Board Memory 56
- DDR2 SDRAM DIMM 57
- DDR2 SDRAM Devices 61
- QDRII+ SRAM 63
- Flash Memory 71
- Power Supply 75
- Power Measurement 76
- Notes to Table 2–60: 78
- Note to Table: 80
- Additional Information Info–3 81
- Typographic Conventions 81
- Info–4 Additional Information 82
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