Altera Stratix III Development Board Manuel d'utilisateur télécharger pdf (Page 20)

2–12 Chapter 2: Board Components

MAX II CPLD

Stratix III 3SL150 Development Board May 2013 Altera Corporation

Reference Manual

L5 FPP configuration data bus bit 5

FPGA_DATA5

2.5 V T24 —

M3 FPP configuration data bus bit 6

FPGA_DATA6

2.5 V T32 —

L4 FPP configuration data bus bit 7

FPGA_DATA7

2.5 V R31 —

C2 FPP configuration clock

FPGA_DCLK

2.5 V AL3 —

E4 FPGA configuration start

FPGA_NCONFIG

2.5 V AE25 —

C3 FPGA configuration status

FPGA_NSTATUS

2.5 V AH28 —

E10 USB command/data select

USB_CMD_DATA

2.5 V Y28 —

B10

USB empty from MAX II device

to Stratix III device

USB_EMPTY

2.5 V AH12 —

USB data from MAX II to

Stratix III bit 0

USB_FD0

2.5 V AE33 —

USB data from MAX II to

Stratix III bit 1

USB_FD1

2.5 V AE31 —

USB data from MAX II to

Stratix III bit 2

USB_FD2

2.5 V AC28 —

USB data from MAX II to

Stratix III bit 3

USB_FD3

2.5 V AA24 —

USB data from MAX II to

Stratix III bit 4

USB_FD4

2.5 V AF34 —

USB data from MAX II to

Stratix III bit 5

USB_FD5

2.5 V AG33 —

USB data from MAX II to

Stratix III bit 6

USB_FD6

2.5 V AA25 —

USB data from MAX II to

Stratix III bit 7

USB_FD7

2.5 V AE32 —

USB full from MAX II to

Stratix III device

USB_FULL

2.5 V AE11 —

J14

USB clock from MAX II to

Stratix III device

USB_IFCLK

2.5 V U1 —

A11

USB read enable from MAX II to

Stratix III device

USB_REN

2.5 V N5 —

USB write enable from MAX II to

Stratix III device

USB_WEN

2.5 V W11 —

L16

Cypress USB pin multiplexed for

I/O or FIFO select

USB_PA5_IF0ADR1

2.5 V — U12 pin 38

Cypress USB pin multiplexed for

I/O or FIFO packet commit

USB_PA6_PKTEND

2.5 V — U12 pin 39

Cypress USB pin multiplexed for

I/O or gate for other FIFO slaves

USB_PA7_SLCSn

2.5 V — U12 pin 40

C13 Cypress/FTDI USB data bus bit 0

USB_PHY_FD0

2.5 V —

U12 pin 18 and U11

pin 25

B16 Cypress/FTDI USB data bus bit 1

USB_PHY_FD1

2.5 V —

U12 pin 19 and U11

pin 24

Table 2–5. MAX II Device Pin-out (Part 5 of 9)

MAX II

Pin Number

Description Schematic Signal Name

I/O

Standard

Stratix III

Number

Other Connections

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 81 82

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Altera Stratix III Development Board Manuel d'utilisateur Page 20

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