Altera Stratix III Development Board Manuel d'utilisateur télécharger pdf (Page 6)

1–2 Chapter 1: Overview

General Description

Stratix III 3SL150 Development Board May 2013 Altera Corporation

Reference Manual

f For more information about:

■ External memory interfaces in Stratix III devices, refer to the External Memory

Interfaces chapter in the Stratix III Device Handbook

■ The Altera DDR and DDR2 SDRAM Controller Compiler MegaCore

function,

refer to the DDR and DDR2 SDRAM Controller Compiler User Guide

■ Power optimization, refer to AN 437: Power Optimization Techniques in Stratix III

FPGAs

■ Altera Video and Image Processing Suite MegaCore functions, refer to the

Video and Image Processing Suite User Guide

Board Component Blocks

The board features the following major component blocks:

■ 1,152-pin Altera Stratix III EP3SL150F FPGA in a ball-grid array (BGA) package

■ 142,000 logic elements (LEs)

■ 5,499 Kbits of memory

■ 384 multiplier blocks

■ Eight phase locked loops (PLLs)

■ 16 global clock networks

■ 736 user I/Os

■ 1.1-V core power

■ 256-pin Altera EPM2210GF256 CPLD in a BGA package

■ 1.8-V core power

■ On-board memory

■ 1-GByte DDR2 SDRAM DIMM

■ 72-Mbit QDRII/+ SRAM

■ 16-MByte DDR2 SDRAM devices

■ Individually addressable

■ 4-MByte SSRAM

■ 64-MByte flash memory

■ FPGA configuration circuitry

■ MAX

II CPLD and flash passive serial configuration

■ On-board USB-Blaster™ circuitry using the Quartus II Programmer

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Altera Stratix III Development Board Manuel d'utilisateur Page 6