Altera DDR SDRAM Controller Manuel d'utilisateur Page 99
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© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
C. HardCopy II Design Walkthrough
This walkthrough explains the additional steps that are needed to use the DDR or
DDR2 SDRAM Controller MegaCore function in a HardCopy II design.
f For details of a complete walkthrough, refer to “DDR & DDR2 SDRAM Controller
Walkthrough” on page 2–9.
You can create a HardCopy II design either with the main target set to a HardCopy II
device and a Stratix II migration device, or with the main revision targeting a Stratix II
device and a companion revision targeting HardCopy II device.
To create a HardCopy II design, follow these steps:
1. Create a new Quartus II project and choose a family, a device, and a companion
device.
1 Altera recommends you choose a –4 speed grade device.
2. Launch IP Toolbench from the MegaWizard Plug-In Manager
3. Parameterize your custom variation.
4. Choose the constraints.
1 HardCopy II devices do not have dedicated hardware for DDR or DDR2
SDRAM capture on as many pins as the Stratix II companion, so there are
less DQS groups available.
5. Generate the variation.
6. Compile the design, which adds placement constraints for critical registers in the
read part of the datapath, and produces a report of the predicted timing margins.
7. The timing report that appears automatically is not available to the HardCopy
Design Centre, therefore add a set of timing constraints to help timing closure, by
running the DDR and DDR2 SDRAM timing wizard (DTW)—choose Tcl scripts
(Tools menu) and choose dtw.
f For more information on the HardCopy II design flow, refer to Back-End Design Flow
for HardCopy Series Devices chapter in volume 2 of the Hardcopy II Device Handbook.
8. To save time re-entering the parameters of the DDR or DDR2 SDRAM Controller
MegaCore function, import the parameters from the <variation
name>_ddr_setting.txt file, by clicking Import… on the third page of the wizard.
9. The DTW also needs an estimate of the t
CO
on the pins that drive the clock to the
DDR or DDR2 SDRAM. When the design has been compiled extract these
automatically in the relevant pane of the wizard.
10. Click Finish. The DTW adds timing constraints to the project, which are preserved
when migrating to HardCopy II devices.
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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