Altera DDR SDRAM Controller Manuel d'utilisateur Page 77
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Noté. / 5. Basé sur avis des utilisateurs
Chapter 3: Functional Description 3–41
MegaCore Verification
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Manual Timings
The manual timing settings do not need to be changed under normal circumstances.
For more information on the manual timing settings, refer to “Manual Timing
Settings” on page A–1.
MegaCore Verification
MegaCore verification involves simulation testing and hardware testing.
Simulation Testing
Altera has carried out extensive random, directed tests with functional test coverage
using industry-standard Denali models to ensure the functionality of the DDR and
DDR2 SDRAM controller. In addition, Altera has carried out a wide variety of gate-
level tests of the DDR and DDR2 SDRAM controllers to verify the post-compilation
functionality of the controllers.
Hardware Testing
Table 3–25 shows the Altera development boards on which Altera hardware tested
the DDR and DDR2 SDRAM controllers.
Table 3–25. Altera Development Boards
Development Board Altera Device Memory Device
Stratix II High-Speed IO Development Board EP2S60F1020C3 Micron DDR2-533 DIMM (MT8HTF3272AG-
53EB3ES)
Stratix II PCI Development Board EP2S60F1020C3 Infineon DDR400 SO-DIMM
(HYS64D32020GDL-5-B)
Stratix PCI Development Board EP1S25F1020C5 Infineon DDR400 SO-DIMM
(HYS64D32020GDL-5-B)
Stratix PCI Development Board, Professional
Edition
EP1S60F1020C6 Micron DDR333 SO-DIMM
(MT8VDDT3264HG-335C2)
Stratix GX High-Speed Development Board EP1SGX25FF1020C6ES Micron DDR400 DIMM
(MT16VDDT3264AG-40BB5)
Internal Stratix Memory Test Board EP1S25F780C5 Micron DDR400 DIMM
(MT16VDDT3264AG-40BB5)
Nios Development Board, Cyclone II
(EP2C35)
EP2C35F672C6 Micron 128-Mbit DDR-333 device
(MT46V16M16-6T)
Cyclone II EP2C35 PCI Development Board EP2C35F672C6 Micron 256-Mbit DDR2-533 device
(MT47H16M16BG-37E)
Cyclone II EP2C35 DSP Development Board EP2C35F672C6 Micron DDR2-533 DIMM (MT8HTF3264AY-
40EB3)
Cyclone Memory Board EP1C6Q240C6 Micron 128-Mbit DDR266 device
(MT46V8M16-75)
Internal Cyclone Memory Test Board EP1C20F400C6 Micron DDR266 DIMM
(MT16VDDT3264AG-265B1)
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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