Altera DDR SDRAM Controller Manuel d'utilisateur Page 6
- Page / 106
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
1–2 Chapter 1: About This Compiler
Features
DDR and DDR2 SDRAM Controller Compiler User Guide March 2009 Altera Corporation
Features
■ Support for industry-standard DDR and DDR2 SDRAM devices and modules
■ 1, 2, 4, or 8 chip-select signals
■ Data mask signals for partial write operations
■ Bank management architecture, which minimizes latency
■ Configurable data width
■ DQS read postamble control logic
■ Free clear-text datapath for use with custom controller
■ Automatic or user-controlled refresh
■ Support for registered DIMMs
■ Optional non-DQS read mode for Stratix and Stratix II side banks
■ IP Toolbench-generated constraint script
■ Quick and easy implementation with example design
■ System timing analysis
■ Support for OpenCore Plus evaluation
■ SOPC Builder ready
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
General Description
The Altera DDR and DDR2 SDRAM Controller Compiler comprises the DDR SDRAM
Controller MegaCore function and the DDR2 SDRAM Controller MegaCore function.
The MegaCore functions provide simplified interfaces to industry-standard DDR
SDRAM and DDR2 SDRAM devices.
The DDR and DDR2 SDRAM Controllers handle the complex aspects of using DDR or
DDR2 SDRAM—initializing the memory devices, managing SDRAM banks, and
keeping the devices refreshed at appropriate intervals. The DDR and DDR2 SDRAM
Controllers translate read and write requests from the local interface into all the
necessary SDRAM command signals.
Other device families (2), (3) No support No support
Notes to Table 1–2:
(1) For new Stratix II designs, use the DDR and DDR2 SDRAM High-Performance Controller.
(2) For more information on support for Stratix III devices with existing designs, contact Altera.
(3) For new Stratix III or Cyclone III designs, use the DDR and DDR2 SDRAM High-Performance Controller.
Table 1–2. Device Family Support (Part 2 of 2)
Device Family
Support
DDR SDRAM DDR2 SDRAM
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
Produits connexes et manuels pour Instruments de mesure Altera DDR SDRAM Controller
Instruments de mesure Altera DSP Development Kit, Cyclone II Edition Getting St Manuel d'utilisateur
(32 pages)
(32 pages)
Instruments de mesure Altera DSP Development Kit, Stratix & Stratix Profess Manuel d'utilisateur
(26 pages)
(26 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.029 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels