Altera DDR SDRAM Controller Manuel d'utilisateur télécharger pdf (Page 84)

A–6

Resynchronization

DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation

Figure A–2 shows the resynchronization registers for Stratix II devices with DQS

capture and optional fed-back clock (refer to Table 3–15 on page 3–35).

Figure A–2. Resynchronization Registers—Stratix II Devices with Fed-back Resynchronization

Notes to Figure A–2:

(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.

(2) IP Toolbench automatically inserts these registers if the design needs them.

clkPLL

DQS

Clocked by delayed DQS Clock

local_rdata

resynch_clk

Reclock resynchronized data

to rising edge registers

(see Note 2)

Fed-back PLL

(Optional)

fedback_

resynch_clk

Intermediate resynchronization registers

(see Note 1)

Resynchronization registers

Capture registers

Clocked by Fed-back Clock

Clocked by Resynchronization Clock

Clocked by System Clock

1 2 ... 79 80 81 82 83 84 85 86 87 88 89 ... 105 106

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Altera DDR SDRAM Controller Manuel d'utilisateur Page 84