Altera DDR SDRAM Controller Manuel d'utilisateur télécharger pdf (Page 97)

B–3

6. The DDR SDRAM wizard automatically creates constraint scripts for the high-

speed DDR SDRAM signals in the top-level design. Therefore, the DDR SDRAM

controller top-level pin names must match what the DDR SDRAM controller

wizard expects. Otherwise, the proper constraints are not made. The following

three settings in the DDR wizard define the pin names to which constraints are

made:

■ Pin name of clock driving memory (+)

■ Pin name of clock driving memory (-)

■ Prefix all DDR SDRAM pins with

Ensure that the DDR SDRAM controller pins at the top-level design adhere to the

naming conventions defined in these settings.

7. For the constraint scripts to work correctly, you must name some 1-bit DDR

SDRAM signals using bus notation at the top-level design, if the top-level design is

a BDF schematic file, which means they require a suffix of [0]. Locate the following

example pins and rename with a [0] suffix:

■ clk_to_sdram_p

■ clk_to_sdram_n

■ sdram_cs_n

■ sdram_cke

The pins now have the following names:

■ clk_to_sdram_p[0]

■ clk_to_sdram_n[0]

■ sdram_cs_n[0]

■ sdram_cke[0]

1 The pin names can change depending on the settings made in step 6, but they must

have the [0] suffix in the top-level schematic.

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Altera DDR SDRAM Controller Manuel d'utilisateur Page 97