Altera DDR SDRAM Controller Manuel d'utilisateur Page 26
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2–16 Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation
Table 2–1. Generated Files (Part 1 of 2) (Note 1) (2)
Filename Description
<variation name>.bsf Quartus II symbol file for the MegaCore function variation. You
can use this file in the Quartus II block diagram editor.
<variation name>.html MegaCore function report file.
<variation name>.vo or .vho VHDL or Verilog HDL IP functional simulation model.
<variation name> .v or .vhd A MegaCore function variation file, which defines a VHDL or
Verilog HDL top-level description of the custom MegaCore
function. Instantiate the entity defined by this file inside of your
design. Include this file when compiling your design in the
Quartus II software.
<variation name>_bb.v Verilog HDL black-box file for the MegaCore function variation.
Use this file when using a third-party EDA tool to synthesize
your design.
<variation name>_auk_ddr_clk_gen.v or .vhd Design file that contains the clock output generators.
<variation name>_auk_ddr_datapath.v or .vhd Design file that instantiates the byte groups and the clock output
generators.
<variation name>_auk_ddr_datapath_pack.v or .vhd A VHDL package, which contains a component that the IP
functional simulation model uses.
<variation name>_auk_ddr_dll.v or .vhd Optional design file that instantiates the Stratix or Stratix II DLL
(Stratix series only).
<variation name>_auk_ddr_dqs_group.v or .vhd Design file that contains the datapath byte groups.
<variation name>_auk_ddr_sdram.v or .vhd Design file that instantiates the controller logic and the datapath
<variation name>_ddr_sdram_vsim.tcl The ModelSim simulation script.
<variation name>_example_driver.v or .vhd The example driver.
<variation name>_example_settings.txt The settings file for your variation, which the add constraints
and the verify timing scripts use.
<variation name>.qip Contains Quartus II project information for your MegaCore
function variations.
<variation name>.v or .vhd (1) Example design file.
add_constraints_for_<variation name>.tcl The add constraints script for the variation.
altera_vhdl_support.vhd A VHDL package that contains functions for the generated
entities. This file may be shared between MegaCore functions.
auto_add_ddr_constraints.tcl The add constraints script, which calls the variation-specific add
constraints scripts.
auto_verify_ddr_timing_constraints.tcl The auto verify timing script, which calls the variation-specific
verify timing scripts.
constraints_out.txt
Log file that IP Toolbench creates while generating the add
constraints script.
ddr_lib_path.tcl The Tcl library path file.
ddr_pll_fb_stratixii.v or .vhd Design file for the Stratix II fedback PLL.
ddr_pll_<device name>.v or .vhd Design file for the system PLL.
generic_ddr_dimm_model.vhd VHDL simulation file.
generic_ddr_sdram.vhd VHDL simulation file.
generic_ddr2_sdram.vhd VHDL simulation file.
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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