Altera DDR SDRAM Controller Manuel d'utilisateur télécharger pdf (Page 85)

A–7

Resynchronization

Figure A–4 shows the resynchronization registers for Stratix II series (non-DQS

mode).

Figure A–3. Resynchronization Registers—Stratix Series, Non-DQS Mode

Notes to Figure A–3:

(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.

(2) IP Toolbench automatically inserts these registers if the design needs them.

clkPLL

Clocked by Capture Clock

local_rdata

resynch_clk

Reclock resynchronized data

to rising edge registers

(see Note 2)

Intermediate resynchronization registers

(see Note 1)

Resynchronization registers

Capture registers

Clocked by Resynchronization Clock

Clocked by System Clock

capture_clk

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 105 106

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Altera DDR SDRAM Controller Manuel d'utilisateur Page 85