Altera CPRI IP Core Manuel d'utilisateur télécharger pdf (Page 191)

Appendix E: Delay Measurement and Calibration E–13

Single-Hop Delay Measurement

December 2013 Altera Corporation CPRI MegaCore Function

User Guide

Figure E–5 shows the Tx path delay components in all CPRI IP core variations except

those that target an Arria V GT device and are configured with the CPRI line rate of

9.8 Gbps. This figure shows the relation between the two Tx paths.

In the CPRI IP core the delay from the AUX interface has a fixed component and a

variable component. In the variations that do not target an Arria V GT device or that

are configured with a CPRI line rate other than 9.8 Gbps, the variable component

results from the Tx elastic buffer and the Tx bitslip delay compensation feature.

The Tx path delay from the AUX interface in most CPRI IP core variations comprises

the following delays:

1. Fixed delay from the AUX interface through the CPRI low-level transmitter to the

Tx elastic buffer. This delay depends on the device family and CPRI data rate. This

delay is the first component of

T_T4

in Figure E–1 on page E–2 and in Table E–6 on

page E–14. Refer to “Fixed Tx Core Delay Component” on page E–14.

2. Variable delay through the Tx elastic buffer, as well as the phase difference

between the core clock and the transceiver

tx_clkout

clock. The “Extended Tx

Delay Measurement” section shows how to calculate the delay in the CPRI Tx

elastic buffer, which includes the phase difference delay.

3. Variable Tx bitslip delay in CPRI RE slaves. Refer to “Tx Bitslip Delay” on

page E–14.

4. Fixed delay from the Tx elastic buffer to the transceiver. This delay depends on the

device family and CPRI line rate. This delay is the second component of

T_T4

Figure E–1 on page E–2 and in Table E–6 on page E–14. Refer to “Fixed Tx Core

Delay Component” on page E–14.

5. Link delay through the transceiver. This delay is

T_txv_TX

in Table E–7 on

page E–16.

Figure E–5. Tx Path Delay from AUX Interface or Through MAP Interface Block to CPRI Link in Most Variations

AxC IF 0

AxC IF n

...

AUX Interface

Data Channels

Transmitter

Transceiver

Transmitter

tx_dataout

Physical Layer

CPRI MAP

Interface Module

AUX

Module

(1)

(5)

(4)

(3)

(2)

1 2 ... 186 187 188 189 190 191 192 193 194 195 196 ... 219 220

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Altera CPRI IP Core Manuel d'utilisateur Page 191

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