Altera CPRI IP Core Manuel d'utilisateur Page 188
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Noté. / 5. Basé sur avis des utilisateurs
E–10 Appendix E: Delay Measurement and Calibration
Single-Hop Delay Measurement
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
6. Calculate the full Rx path delay to the AUX interface by adding the values you
derived in step 1 through step 5. For the example, calculate the Rx path delay as
follows:
Rx path delay = T_txv_RX + <delay through Rx Receive buffer>
+ <
rx_byte_delay
value> + <
cal_pointer
value>
+ <delay to AUX IF>
= 5.7 + 33.236 + 0 + 3 + 5
cpri_clkout
clock cycles
= 46.936
cpri_clkout
clock cycles
Arria V GT 9.8 Gbps
Arria V GT 9.8 Gbps variations use a soft PCS, and are a special case. The following
sections describe the unique differences of these variations.
Rx Path Delay Components
Figure E–4 shows the Rx path delay components in a CPRI IP core variation that
targets an Arria V GT device and was originally configured with the CPRI line rate of
9.8 Gbps. This figure illustrates the Rx path delay components in Arria V GT
variations whose CPRI line rate was auto-negotiated down from the configured CPRI
line rate of 9.8 Gbps to a lower line rate, as well.
The figure shows the relation between the two Rx paths, the path through the AUX
module and the path through the MAP interface module but not through the AxC
interface blocks.
In the CPRI IP core variations that target an Arria V GT device, and were configured
with a with a CPRI line rate of 9.8 Gbps, the link delay (1.) includes the following
delays:
a. Fixed delay through the PMA configured with the Altera Native PHY IP core.
b. Delay through an Rx buffer between the PMA and the PCS. The “Extended Rx
Delay Measurement” section shows how to calculate this delay.
c. Fixed delay through the PCS.
d. Variable delay introduced by round-trip delay calibration feature. Refer to
“Round-Trip Calibration Delay” on page E–7 and “Dynamic Pipelining for
Automatic Round-Trip Delay Calibration” on page E–19. This delay
component is common to all CPRI IP core variations.
The following sections describe the individual delays and how to calculate them.
Figure E–4. Rx Path Delay in Arria V GT Variations Configured with a CPRI Line Rate of 9.8 Gbps
AxC IF 0
AxC IF n
...
AUX Interface
Data Channels
PMA
Receiver
rx_datain
Physical Layer
CPRI MAP
Interface Module
AUX
Module
Rx Buffer
(1a)
PCS
(1c)(1b)
(2)
(2)
(1d)
- User Guide 1
- CPRI MegaCore Function 1
- Contents 3
- Chapter 5. Testing Features 4
- ContentsContents v 5
- General Description 8
- CPRI IP Core Features 10
- Device Family Support 11
- MegaCore Verification 12
- Release Information 14
- Installation and Licensing 15
- OpenCore Plus Evaluation 16
- 2. Getting Started 17
- Specifying Parameters 18
- Simulation Files 19
- Simulating the Design 20
- Supporting the Transceivers 21
- Specifying Constraints 21
- 3. Parameter Settings 25
- Operation Mode Parameter 26
- Line Rate Parameter 26
- Enable Autorate Negotiation 27
- Rx Elastic Buffer Depth 27
- Include MAC Block 28
- Include HDLC Block 29
- Mapping Mode 29
- Application Layer Parameters 30
- Words” on page 4–42 32
- 4. Functional Description 33
- Architecture Overview 34
- CPRI IP Core Clocks 35
- Clocking Structure 36
- Notes to Table 4–2: 42
- Reset Requirements 43
- MegaCore 44
- Function 44
- MAP Interface Mapping Modes 45
- Basic AxC Mapping Mode 46
- MAP Interface 47
- Note to Table 4–5: 49
- Note to Table 4–6: 49
- Advanced AxC Mapping Modes 50
- MAP Receiver Interface 50
- Notes to Table 4–7: 51
- MAP Receiver in FIFO Mode 52
- MAP Transmitter Interface 56
- Notes to Table 4–10: 57
- MAP Transmitter in FIFO Mode 58
- Auxiliary Interface 62
- AUX Receiver Module 63
- Avalon-ST 32-bit interface 64
- AUX Transmitter Module 66
- Note to Figure 4–19: 67
- MII Transmitter 70
- MII Receiver 71
- CPU Interface 73
- Control Word Order 78
- Transmitting Ethernet Traffic 80
- Receiving Ethernet Traffic 81
- Accessing the HDLC Channel 82
- Note to Table 4–15: 83
- Features 84
- Physical Layer Architecture 84
- Receiver 85
- High-Speed Transceiver 86
- Rx Elastic Buffer 86
- Descrambling 87
- Frame Synchronization 87
- Alarm Indications 88
- Reset Control Word 89
- Transmitter 90
- Scrambling 91
- Tx Elastic Buffer 91
- External Loopback 93
- CPRI IP Core 93
- Internal Reverse Loopback 94
- Physical Layer Loopback Mode 94
- (1) (2) (3) 96
- MAP Receiver Signals 99
- 6–2 Chapter 6: Signals 100
- MAP Interface Signals 100
- MAP Transmitter Signals 101
- 6–4 Chapter 6: Signals 102
- Auxiliary Interface Signals 103
- AUX Receiver Signals 104
- AUX Transmitter Signals 105
- 6–8 Chapter 6: Signals 106
- Extended Rx Status Signals 107
- CPRI MII Receiver Signals 108
- CPRI MII Transmitter Signals 108
- CPU Interface Signals 109
- CPRI Data Signals 110
- Layer 1 Error Signal 111
- Autorate Negotiation Signals 111
- 6–14 Chapter 6: Signals 112
- Physical Layer Signals 112
- Transceiver Signals 113
- 6–16 Chapter 6: Signals 114
- Note to Table 6–14: 115
- 6–18 Chapter 6: Signals 116
- 7. Software Interface 117
- Note to Table 7–5: 119
- CPRI_HW_RESET 123
- register, refer to “Reset 123
- Requirements” on page 4–11 123
- Note to Table 7–13: 124
- Note to Table 7–16: 125
- Note to Table 7–17: 126
- Note to Table 7–20: 126
- Notes to Table 7–21: 127
- Notes to Table 7–28: 130
- Notes to Table 7–29: 130
- Note to Table 7–32: 133
- Note to Table 7–33: 133
- Note to Table 7–34: 133
- Note to Table 7–35: 134
- Note to Table 7–36: 134
- Notes to Table 7–37: 135
- Notes to Table 7–38: 135
- Notes to Table 7–39: 136
- Notes to Table 7–40: 136
- Note to Table 7–45: 137
- Ethernet Registers 138
- HDLC Registers 143
- Note to Figure 8–1: 150
- Test Sequence 151
- Running the Testbench 153
- A. Initialization Sequence 155
- Negotiation 157
- Notes for Figure B–1: 158
- Running Autorate Negotiation 159
- Notes to Table C–3: 167
- D. Advanced AxC Mapping Modes 173
- Fifteen-Bit Width Mode 175
- Sixteen-Bit Width Mode 176
- Note to Figure D–2: 177
- Delay Requirements 179
- RE SlaveREC Master 180
- Rx Path Delay 181
- Most CPRI IP Core Variations 181
- Single-Hop Delay Measurement 182
- Notes to Table E–1: 183
- Notes to Table E–2: 184
- Notes to Table E–3: 186
- Arria V GT 9.8 Gbps 188
- Notes to Table E–4: 189
- Tx Path Delay 190
- Note to Table E–6: 192
- T_txv_TX 194
- in Figure E–1 on page E–2 194
- Round-Trip Delay 196
- Round-Trip Cable Delay 196
- Families 202
- Round-Trip Delay Calculation 205
- Multi-Hop Delay Measurement 206
- Additional Information 213
- Document Revision History 214
- How to Contact Altera 218
- Typographic Conventions 218
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