Altera CPRI IP Core Manuel d'utilisateur Page 175
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Noté. / 5. Basé sur avis des utilisateurs
Appendix D: Advanced AxC Mapping Modes D–3
Advanced Mapping Mode Similarities and Differences
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
1 Some table entries are not available, depending on the CPRI line rate and on K. In the
example illustrated in Figure D–2, the table entries 7 and 15 are not available.
In 16-bit mode in all advanced mapping modes, and in 15-bit mode in advanced
mapping mode 2’b01, you can use the
width
field to specify the size of the sample that
starts in the bit position indicated in the
position
field, allowing you to pack a second
sample immediately following the first sample in the timeslot, or to specify a sample
width larger than the timeslot. In the case of a sample that spills into the following
timeslot, you must enable the following timeslot in the Rx or Tx mapping table.
In 15-bit width mode in advanced mapping modes 2’b10 and 2’b11, you must set
width
to the value of 15 (indicating a 30-bit IQ sample), and you must set
position
to
specify the offset of the next available bit in the current 32-bit timeslot, because the IQ
samples are packed in the timeslots with no intervening spare bits.
You can calculate the number of timeslots that correspond to a CPRI frame. Only the
data bytes pass through the AxC interface; the control bytes in a CPRI frame do not
pass through the AxC interface. Refer to the Number of Bits column in Table 4–5 on
page 4–17 or Table 4–6 on page 4–17 for the number of data bits in a CPRI frame
at each CPRI line data rate. The calculation depends on the presence and values of any
position
offsets, on whether the CPRI IP core is in 15-bit width mode or in 16-bit
width mode, and on how remainder bytes are handled. The following discussion
focuses on the cases with
position
fields all set to zero. You can increment the
timeslot counts as needed to accommodate unused leading timeslot bits specified
with
position
offsets.
Fifteen-Bit Width Mode
In 15-bit width mode, you either pack the 30-bit data samples in the 32-bit words (in
advanced mapping modes Advanced 2 (2’b10) and Advanced 3 (2’b11)), or you
selectively allow gaps, specifying them with the
position
and
width
fields of the table
entry (in the new Advanced 1 mapping mode (2’b01)). In 15-bit width mode,
advanced AxC mapping modes 2’b10 and 2’b11 act identically, packing the data into
consecutive bits. Because the number of bits in the IQ data block of every CPRI frame
is a multiple of 30, packed 15-bit I- and Q-samples fill an AxC container—and one or
more CPRI frames—with no spare bytes remaining. However, in the Advanced 1
mapping mode, you can specify an offset in the
position
field, potentially leaving
spare bytes in the IQ data block.
Figure D–1 shows the contrast between these advanced mapping modes. In this 15-bit
mode example, the CPRI data rate is 1228.8 Gbps and the value of K is two. For a
CPRI IP core running at CPRI data rate 1228.8 Gbps, the number of data bits in a CPRI
basic frame is 240. (Refer to Table 4–6 on page 4–17). If K (specified in the
K
field of the
- User Guide 1
- CPRI MegaCore Function 1
- Contents 3
- Chapter 5. Testing Features 4
- ContentsContents v 5
- General Description 8
- CPRI IP Core Features 10
- Device Family Support 11
- MegaCore Verification 12
- Release Information 14
- Installation and Licensing 15
- OpenCore Plus Evaluation 16
- 2. Getting Started 17
- Specifying Parameters 18
- Simulation Files 19
- Simulating the Design 20
- Supporting the Transceivers 21
- Specifying Constraints 21
- 3. Parameter Settings 25
- Operation Mode Parameter 26
- Line Rate Parameter 26
- Enable Autorate Negotiation 27
- Rx Elastic Buffer Depth 27
- Include MAC Block 28
- Include HDLC Block 29
- Mapping Mode 29
- Application Layer Parameters 30
- Words” on page 4–42 32
- 4. Functional Description 33
- Architecture Overview 34
- CPRI IP Core Clocks 35
- Clocking Structure 36
- Notes to Table 4–2: 42
- Reset Requirements 43
- MegaCore 44
- Function 44
- MAP Interface Mapping Modes 45
- Basic AxC Mapping Mode 46
- MAP Interface 47
- Note to Table 4–5: 49
- Note to Table 4–6: 49
- Advanced AxC Mapping Modes 50
- MAP Receiver Interface 50
- Notes to Table 4–7: 51
- MAP Receiver in FIFO Mode 52
- MAP Transmitter Interface 56
- Notes to Table 4–10: 57
- MAP Transmitter in FIFO Mode 58
- Auxiliary Interface 62
- AUX Receiver Module 63
- Avalon-ST 32-bit interface 64
- AUX Transmitter Module 66
- Note to Figure 4–19: 67
- MII Transmitter 70
- MII Receiver 71
- CPU Interface 73
- Control Word Order 78
- Transmitting Ethernet Traffic 80
- Receiving Ethernet Traffic 81
- Accessing the HDLC Channel 82
- Note to Table 4–15: 83
- Features 84
- Physical Layer Architecture 84
- Receiver 85
- High-Speed Transceiver 86
- Rx Elastic Buffer 86
- Descrambling 87
- Frame Synchronization 87
- Alarm Indications 88
- Reset Control Word 89
- Transmitter 90
- Scrambling 91
- Tx Elastic Buffer 91
- External Loopback 93
- CPRI IP Core 93
- Internal Reverse Loopback 94
- Physical Layer Loopback Mode 94
- (1) (2) (3) 96
- MAP Receiver Signals 99
- 6–2 Chapter 6: Signals 100
- MAP Interface Signals 100
- MAP Transmitter Signals 101
- 6–4 Chapter 6: Signals 102
- Auxiliary Interface Signals 103
- AUX Receiver Signals 104
- AUX Transmitter Signals 105
- 6–8 Chapter 6: Signals 106
- Extended Rx Status Signals 107
- CPRI MII Receiver Signals 108
- CPRI MII Transmitter Signals 108
- CPU Interface Signals 109
- CPRI Data Signals 110
- Layer 1 Error Signal 111
- Autorate Negotiation Signals 111
- 6–14 Chapter 6: Signals 112
- Physical Layer Signals 112
- Transceiver Signals 113
- 6–16 Chapter 6: Signals 114
- Note to Table 6–14: 115
- 6–18 Chapter 6: Signals 116
- 7. Software Interface 117
- Note to Table 7–5: 119
- CPRI_HW_RESET 123
- register, refer to “Reset 123
- Requirements” on page 4–11 123
- Note to Table 7–13: 124
- Note to Table 7–16: 125
- Note to Table 7–17: 126
- Note to Table 7–20: 126
- Notes to Table 7–21: 127
- Notes to Table 7–28: 130
- Notes to Table 7–29: 130
- Note to Table 7–32: 133
- Note to Table 7–33: 133
- Note to Table 7–34: 133
- Note to Table 7–35: 134
- Note to Table 7–36: 134
- Notes to Table 7–37: 135
- Notes to Table 7–38: 135
- Notes to Table 7–39: 136
- Notes to Table 7–40: 136
- Note to Table 7–45: 137
- Ethernet Registers 138
- HDLC Registers 143
- Note to Figure 8–1: 150
- Test Sequence 151
- Running the Testbench 153
- A. Initialization Sequence 155
- Negotiation 157
- Notes for Figure B–1: 158
- Running Autorate Negotiation 159
- Notes to Table C–3: 167
- D. Advanced AxC Mapping Modes 173
- Fifteen-Bit Width Mode 175
- Sixteen-Bit Width Mode 176
- Note to Figure D–2: 177
- Delay Requirements 179
- RE SlaveREC Master 180
- Rx Path Delay 181
- Most CPRI IP Core Variations 181
- Single-Hop Delay Measurement 182
- Notes to Table E–1: 183
- Notes to Table E–2: 184
- Notes to Table E–3: 186
- Arria V GT 9.8 Gbps 188
- Notes to Table E–4: 189
- Tx Path Delay 190
- Note to Table E–6: 192
- T_txv_TX 194
- in Figure E–1 on page E–2 194
- Round-Trip Delay 196
- Round-Trip Cable Delay 196
- Families 202
- Round-Trip Delay Calculation 205
- Multi-Hop Delay Measurement 206
- Additional Information 213
- Document Revision History 214
- How to Contact Altera 218
- Typographic Conventions 218
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