Altera CPRI IP Core Manuel d'utilisateur Page 136
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
7–20 Chapter 7: Software Interface
MAP Interface and AUX Interface Configuration Registers
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
start_rx_offset_x
[7:0] RW
Basic frame number for start of
cpri_rx_start
synchronization output.
8’h0
Notes to Table 7–39:
(1) In synchronous buffer mode, the offset specified in this register must follow (be greater than) the offset specified in the
CPRI_MAP_OFFSET_RX
register described in Table 7–37. For an explanation of this requirement and an overview of the considerations in determining the value in this
register, refer to “MAP Receiver in Synchronous Buffer Mode” on page 4–21 and to “Rx Path Delay” on page E–3. If your register values do not
comply with this requirement, your CPRI IP core will experience data corruption on the active data channels in the synchronous buffer
synchronization mode.
(2) This register does not participate in data transfer synchronization on the antenna-carrier interfaces in FIFO mode or in the internally-clocked
mode.
Table 7–39. CPRI_START_OFFSET_RX—Rx Start Frame Offset
(1), (2)
—Offset: 0x120 (Part 2 of 2)
Field Bits Access Function Default
Table 7–40. CPRI_START_OFFSET_TX—Tx Start Frame Offset
(1), (2)
—Offset: 0x124
Field Bits Access Function Default
RSRV
[31:25] UR0 Reserved.
7'h0
start_tx_hf_resync
[24] RW
Enables synchronization every hyperframe instead of every
radio frame. When asserted, the
start_tx_offset_z
field is
ignored.
1’h0
RSRV
[23:22] UR0 Reserved.
2'h0
start_tx_offset_seq
[21:16] RW
Sequence number for start of
cpri_tx_start
synchronization output.
6’h0
start_tx_offset_z
[15:8] RW
Hyperframe number for start of
cpri_tx_start
synchronization output.
8’h0
start_tx_offset_x
[7:0] RW
Basic frame number for start of
cpri_tx_start
synchronization output.
8’h0
Notes to Table 7–40:
(1) In synchronous buffer mode, the offset specified in this register must precede (be less than) the offset specified in the
CPRI_MAP_OFFSET_TX
register described in Table 7–38. For an explanation of this requirement and an overview of the considerations in determining the value in this
register, refer to “MAP Transmitter in Synchronous Buffer Mode” on page 4–27 and to “Tx Path Delay” on page E–12. If your register values do
not comply with this requirement, your CPRI IP core will experience data corruption on the active data channels in the synchronous buffer
synchronization mode.
(2) This register does not participate in data transfer synchronization on the antenna-carrier interfaces in FIFO mode or in the internally-clocked
mode.
Table 7–41. CPRI_MAP_RX_READY_THR—CPRI Mapping Rx Ready Threshold—Offset: 0x128
Field Bits Access Function Default
RSRV
[31:4] UR0 Reserved.
28’h0
map_rx_ready_thr
[3:0] RW
Threshold for assertion of the
mapN_rx_valid
signal in FIFO
mode, for all data channels
N
. The
mapN_rx_valid
signal is
asserted only when the MAP Rx buffer for data channel
N
fills
beyond this threshold value. All the MAP Rx buffers have the same
depth, 16.
4’h8
- User Guide 1
- CPRI MegaCore Function 1
- Contents 3
- Chapter 5. Testing Features 4
- ContentsContents v 5
- General Description 8
- CPRI IP Core Features 10
- Device Family Support 11
- MegaCore Verification 12
- Release Information 14
- Installation and Licensing 15
- OpenCore Plus Evaluation 16
- 2. Getting Started 17
- Specifying Parameters 18
- Simulation Files 19
- Simulating the Design 20
- Supporting the Transceivers 21
- Specifying Constraints 21
- 3. Parameter Settings 25
- Operation Mode Parameter 26
- Line Rate Parameter 26
- Enable Autorate Negotiation 27
- Rx Elastic Buffer Depth 27
- Include MAC Block 28
- Include HDLC Block 29
- Mapping Mode 29
- Application Layer Parameters 30
- Words” on page 4–42 32
- 4. Functional Description 33
- Architecture Overview 34
- CPRI IP Core Clocks 35
- Clocking Structure 36
- Notes to Table 4–2: 42
- Reset Requirements 43
- MegaCore 44
- Function 44
- MAP Interface Mapping Modes 45
- Basic AxC Mapping Mode 46
- MAP Interface 47
- Note to Table 4–5: 49
- Note to Table 4–6: 49
- Advanced AxC Mapping Modes 50
- MAP Receiver Interface 50
- Notes to Table 4–7: 51
- MAP Receiver in FIFO Mode 52
- MAP Transmitter Interface 56
- Notes to Table 4–10: 57
- MAP Transmitter in FIFO Mode 58
- Auxiliary Interface 62
- AUX Receiver Module 63
- Avalon-ST 32-bit interface 64
- AUX Transmitter Module 66
- Note to Figure 4–19: 67
- MII Transmitter 70
- MII Receiver 71
- CPU Interface 73
- Control Word Order 78
- Transmitting Ethernet Traffic 80
- Receiving Ethernet Traffic 81
- Accessing the HDLC Channel 82
- Note to Table 4–15: 83
- Features 84
- Physical Layer Architecture 84
- Receiver 85
- High-Speed Transceiver 86
- Rx Elastic Buffer 86
- Descrambling 87
- Frame Synchronization 87
- Alarm Indications 88
- Reset Control Word 89
- Transmitter 90
- Scrambling 91
- Tx Elastic Buffer 91
- External Loopback 93
- CPRI IP Core 93
- Internal Reverse Loopback 94
- Physical Layer Loopback Mode 94
- (1) (2) (3) 96
- MAP Receiver Signals 99
- 6–2 Chapter 6: Signals 100
- MAP Interface Signals 100
- MAP Transmitter Signals 101
- 6–4 Chapter 6: Signals 102
- Auxiliary Interface Signals 103
- AUX Receiver Signals 104
- AUX Transmitter Signals 105
- 6–8 Chapter 6: Signals 106
- Extended Rx Status Signals 107
- CPRI MII Receiver Signals 108
- CPRI MII Transmitter Signals 108
- CPU Interface Signals 109
- CPRI Data Signals 110
- Layer 1 Error Signal 111
- Autorate Negotiation Signals 111
- 6–14 Chapter 6: Signals 112
- Physical Layer Signals 112
- Transceiver Signals 113
- 6–16 Chapter 6: Signals 114
- Note to Table 6–14: 115
- 6–18 Chapter 6: Signals 116
- 7. Software Interface 117
- Note to Table 7–5: 119
- CPRI_HW_RESET 123
- register, refer to “Reset 123
- Requirements” on page 4–11 123
- Note to Table 7–13: 124
- Note to Table 7–16: 125
- Note to Table 7–17: 126
- Note to Table 7–20: 126
- Notes to Table 7–21: 127
- Notes to Table 7–28: 130
- Notes to Table 7–29: 130
- Note to Table 7–32: 133
- Note to Table 7–33: 133
- Note to Table 7–34: 133
- Note to Table 7–35: 134
- Note to Table 7–36: 134
- Notes to Table 7–37: 135
- Notes to Table 7–38: 135
- Notes to Table 7–39: 136
- Notes to Table 7–40: 136
- Note to Table 7–45: 137
- Ethernet Registers 138
- HDLC Registers 143
- Note to Figure 8–1: 150
- Test Sequence 151
- Running the Testbench 153
- A. Initialization Sequence 155
- Negotiation 157
- Notes for Figure B–1: 158
- Running Autorate Negotiation 159
- Notes to Table C–3: 167
- D. Advanced AxC Mapping Modes 173
- Fifteen-Bit Width Mode 175
- Sixteen-Bit Width Mode 176
- Note to Figure D–2: 177
- Delay Requirements 179
- RE SlaveREC Master 180
- Rx Path Delay 181
- Most CPRI IP Core Variations 181
- Single-Hop Delay Measurement 182
- Notes to Table E–1: 183
- Notes to Table E–2: 184
- Notes to Table E–3: 186
- Arria V GT 9.8 Gbps 188
- Notes to Table E–4: 189
- Tx Path Delay 190
- Note to Table E–6: 192
- T_txv_TX 194
- in Figure E–1 on page E–2 194
- Round-Trip Delay 196
- Round-Trip Cable Delay 196
- Families 202
- Round-Trip Delay Calculation 205
- Multi-Hop Delay Measurement 206
- Additional Information 213
- Document Revision History 214
- How to Contact Altera 218
- Typographic Conventions 218
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