Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur Page 91
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Mentor Verification IP AE AXI4-Lite User Guide, V10.3
91
April 2014
Chapter 5
SystemVerilog Monitor BFM
This chapter describes the SystemVerilog monitor BFM. Each BFM has an API that contains
tasks and functions to configure the BFM and to access the dynamic Transaction Record during
the lifetime of a transaction.
Inline Monitor Connection
The connection of a monitor BFM to a test environment differs from that of a master and slave
BFM. It is wrapped in an inline monitor interface and connected inline between a master and
slave, as shown in Figure 5-1. It has separate master and slave ports and monitors protocol
traffic between a master and slave. The monitor itself then has access to all the facilities
provided by the monitor BFM.
Figure 5-1. Inline Monitor Connection Diagram
Monitor BFM Protocol Support
The AXI4-Lite monitor BFM supports the AMBA AXI4 protocol with restrictions described in
“Protocol Restrictions” on page 17.
Monitor Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following monitor
BFM API timing and events.
The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the monitor BFM does not contain any timescale,
SlaveMaster
Inline monitor
Master portSlave port
Monitor
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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