Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur télécharger pdf (Page 397)

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101

Mentor Verification IP AE AXI4-Lite User Guide, V10.3

397

April 2014

Appendix C

VHDL Test Programs

This appendix contains VHDL test programs, one for the master BFM and the other for the

slave BFM.

AXI4-Lite VHDL Master BFM Test Program

The following code example contains a simple master test program that shows the master BFM

API being used to communicate with a slave and create stimulus. This test program is discussed

further in “SystemVerilog Tutorials” on page 115.

*************************************************************************

-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS

-- THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS

-- SUBJECT TO LICENSE TERMS.

*************************************************************************

-- This is a simple example of an AXI4 master to demonstrate the

mgc_axi4_master BFM configured as axi4lite usage.

-- This master performs a directed test, initiating 4 sequential

writes, followed by 4 sequential reads.

-- It then verifies that the data read out matches the data written.

library ieee ;

use ieee.std_logic_1164.all;

library work;

use work.all;

use work.mgc_axi4_bfm_pkg.all;

use std.textio.all;

use ieee.std_logic_textio.all;

entity master_test_program is

generic (AXI4_ADDRESS_WIDTH : integer := 32;

AXI4_RDATA_WIDTH : integer := 32;

AXI4_WDATA_WIDTH : integer := 32;

index : integer range 0 to 511 :=0

);

end master_test_program;

architecture master_test_program_a of master_test_program is

1 2 ... 392 393 394 395 396 397 398 399 400 401 402 ... 412 413

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