Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur Page 67
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SystemVerilog Slave BFM
Slave Assertions
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
67
April 2014
1.
Refer to Slave Timing and Events for details of simulator time-steps.
Slave Assertions
Each slave BFM performs protocol error checking using the built-in assertions.
Note
The built-in BFM assertions are independent of programming language and simulator.
Assertion Configuration
By default, all built-in assertions are enabled in the slave AXI4-Lite BFM. To globally disable
them in the slave BFM, use the set_config() command as the following example illustrates:
set_config(AXI4_CONFIG_ENABLE_ALL_ASSERTIONS,0)
Alternatively, you can disable individual built-in assertions by using a sequence of get_config()
and set_config() commands on the respective assertion. For example, to disable assertion
checking for the AWADDR signal changing between the AWVALID and AWREADY
handshake signals, use the following sequence of commands:
// Define a local bit vector to hold the value of the assertion bit vector
bit [255:0] config_assert_bitvector;
AXI4_CONFIG_NUM_OUTSTANDING_
WR_PHASE
Holds the number of outstanding write
phases from the master that can be
processed by the slave.
Default = 0.
AXI4_CONFIG_NUM_OUTSTANDING_
RD_PHASE
Holds the number of outstanding read
phases to the master that can be
processed by the slave.
Default = 0.
Error Detection
AXI4_CONFIG_ENABLE_ALL_
ASSERTIONS
Global enable/disable of all assertion
checks in the BFM.
0 = disabled
1 = enabled (default)
AXI4_CONFIG_ENABLE_ASSERTION Individual enable/disable of assertion
check in the BFM.
0 = disabled
1 = enabled (default)
Table 4-2. Slave BFM Configuration (cont.)
Configuration Field Description
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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