Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur télécharger pdf (Page 116)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3

116

SystemVerilog Tutorials

Verifying a Slave DUT

April 2014

In this example, the master test program also compares the written data with that read back from

the slave DUT, reporting the result of the comparison.

A top-level file instantiates and connects all the components required to test and monitor the

DUT, and controls the system clock (ACLK) and reset (ARESETn) signals.

BFM Master Test Program

A master test program using the master BFM API is capable of creating a wide range of

stimulus scenarios to verify a slave DUT. However, this tutorial restricts the master BFM

stimulus to write transactions followed by read transactions to the same address, and then

compares the read data with the previously written data. For a complete code listing of this

master test program, refer to “SystemVerilog AXI4-Lite Master BFM Test Program” on

page 385

The master test program contains the following elements:

• A Configuration and Initialization that creates and executes read and write transactions.

• Tasks handle_write_resp_ready() and handle_read_data_ready() to handle the delay of

the write response channel BREADY signal and the read data channel RREADY

signals, respectively.

• Variables m_wr_resp_phase_ready_delay and m_rd_data_phase_ready_delay to set the

delay of the BREADY and RREADY signals

• A master_ready_delay_mode variable to configure the behavior of the handshake

signals *VALID to *READY delay.

The following sections describe the main tasks and variables.

master_ready_delay_mode

The master_ready_delay_mode variable holds the configuration that defines the starting point

of any delay applied to the RREADY and BREADY signals. It can be configured to the

enumerated type values of AXI4_VALID2READY (default) or AXI4_TRANS2READY.

The default configuration (master_ready_delay_mode = AXI4_VALID2READY) corresponds

to the delay measured from the positive edge of ACLK when *VALID is asserted. Figure 6-2

shows how to achieve a *VALID before *READY handshake, respectively.

1 2 ... 111 112 113 114 115 116 117 118 119 120 121 ... 412 413

Pas de commentaire

Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur Page 116