Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuel d'utilisateur Page 51
- Page / 196
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
error appears as a 66-bit error block that consists of eight /E/ characters (EBLOCK_T) in the Ethernet
frame.
To direct the IP core to insert a TX error in a packet, the client should assert the TX error insertion signal
as follows, depending on the TX client interface:
• On the Avalon-ST TX client interface, assert the l<n>_tx_error signal in the EOP cycle of the packet.
• On the custom streaming TX client interface, assert bit N of the tx_error[<w>-1:0] signal in the
same cycle in which bit N of din_eop[<w>-1:0] is asserted.
The IP core overwrites Ethernet frame data with an EBLOCK_T error block when it transmits the
Ethernet frame that corresponds to the packet EOP.
This feature supports test amd debug of your IP core. In loopback mode, when the IP core receives a
deliberately errored packet on the Ethernet link, the IP core recognizes it as a malformed packet.
Related Information
LL 40-100GbE IP Core Malformed Packet Handling on page 3-17
Low Latency 40-100GbE IP Core TX Data Bus Interfaces
This section describes the TX data bus at the user interface and includes the following topics:
Low Latency 40-100GbE IP Core User Interface Data Bus on page 3-6
Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) on page 3-7
Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) on
page 3-10
Bus Quantization Effects With Adapters on page 3-11
User Interface to Ethernet Transmission on page 3-12
Low Latency 40-100GbE IP Core User Interface Data Bus
Table 3-1: User Interface Width Depends on IP Core Variation
The Low Latency 40-100GbE IP core provides two different client interfaces: the Avalon-ST interface and a
custom interface. The Avalon-ST interface requires adapters and the custom streaming interface does not require
adapters.
Client Interface
Data Bus Width (Bits)
LL 40GbE IP Core LL 100GbE IP Core
Custom streaming interface (no
adapters)
128 256
Avalon-ST interface (with
adapters)
256 512
3-6
Low Latency 40-100GbE IP Core TX Data Bus Interfaces
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
Produits connexes et manuels pour Instruments de mesure Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore
Instruments de mesure Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur
(413 pages)
(413 pages)
Instruments de mesure Altera Mentor Verification IP Altera Edition AMBA AXI4-St Manuel d'utilisateur
(231 pages)
(231 pages)
Instruments de mesure Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manuel d'utilisateur
(783 pages)
(783 pages)
Instruments de mesure Altera PCI Development Kit, Cyclone II Edition Getting St Manuel d'utilisateur
(40 pages)
(40 pages)
Instruments de mesure Altera PCI Express Development Kit, Stratix II GX Edition Manuel d'utilisateur
(36 pages)
(36 pages)
Panasonic TXD32LF72F manuali
Manuali dei proprietari e guide per l'utente per TV a cristalli liquidi Panasonic TXD32LF72F.
We fornisce 2 manuali pdf Panasonic TXD32LF72F per scaricare gratuitamente in base al tipo di documento: Istruzioni per gli Interventi
Commentaires sur ces manuels