Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuel d'utilisateur Page 24
- Page / 196
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Parameter Type Range Default
Setting
Parameter Description
Status clock
rate
Frequenc
y range
100–162
MHz
100
MHz
Sets the expected incoming clk_status frequency.
The input clock frequency must match the frequency
you specify for this parameter.
The IP core is configured with this information:
• To ensure the IP core measures the link fail inhibit
time accurately.Determines the value of the Link
Fail Inhibit timer (IEEE 802.3 clause 73.10.2)
correctly.
• If clk_status frequency is not 100 MHz, to
adjust the PHY clock monitors to report accurate
frequency information.
This parameter determines the PHY Management
clock (MGMT_CLK) frequency in MHz parameter
of the underlying 10GBASE-KR PHY IP core.
However, the default value of the Status clock rate
parameter is different.
Auto-Negotiation
Enable Auto-
Negotiation
Boolean • True
• False
True If this parameter is turned on, the IP core includes
logic to implement auto-negotiation as defined in
Clause 73 of IEEE Std 802.3ap–2007. If this parameter
is turned off, the IP core does not include auto-
negotiation logic and cannot perform auto-negotia‐
tion.
Currently the IP core can only negotiate to KR4
mode.
Link fail inhibit
time for 40Gb
Ethernet
Integer
(Unit:
ms)
500–510
ms
504 ms Specifies the time before link status is set to FAIL or
OK. A link fails if the time duration specified by this
parameter expires before link status is set to OK. For
more information, refer to Clause 73 Auto-Negotia‐
tion for Backplane Ethernet in IEEE Standard
802.3ap–2007.
The 40GBASE-KR4 IP core asserts the rx_pcs_ready
signal to indicate link status is OK.
Auto-Negotia‐
tion Master
String • Lane 0
• Lane 1
• Lane 2
• Lane 3
Lane 0 Selects the master channel for auto-negotiation.
Pause ability–
C0
Boolean • True
• False
True If this parameter is turned on, the IP core indicates
on the Ethernet link that it supports symmetric
pauses as defined in Annex 28B of Section 2 of IEEE
Std 802.3–2008.
2-10
IP Core Parameters
UG-01172
2015.05.04
Altera Corporation
Getting Started
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
Produits connexes et manuels pour Instruments de mesure Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore
Instruments de mesure Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Manuel d'utilisateur
(413 pages)
(413 pages)
Instruments de mesure Altera Mentor Verification IP Altera Edition AMBA AXI4-St Manuel d'utilisateur
(231 pages)
(231 pages)
Instruments de mesure Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manuel d'utilisateur
(783 pages)
(783 pages)
Instruments de mesure Altera PCI Development Kit, Cyclone II Edition Getting St Manuel d'utilisateur
(40 pages)
(40 pages)
Instruments de mesure Altera PCI Express Development Kit, Stratix II GX Edition Manuel d'utilisateur
(36 pages)
(36 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.023 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels