Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuel d'utilisateur Page 11

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IP Core
Variation
A B C D E F
Parameter
Enable
1588 PTP
On
Enable
link fault
generatio
n
On On
Enable
TX CRC
insertion
On On On On On
Enable
preamble
passthrou
gh
On On
Enable
alignmen
t EOP on
FCS word
On On On On On
Enable
TX
statistics
On On On On On
Enable
RX
statistics
On On On On On
Enable
KR4
On On
Include
FEC
sublayer
On
Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores
Resource utilization changes depending on the parameter settings you specify in the Low Latency
40-100GbE parameter editor. For example, if you turn on pause functionality or statistics counters in the
LL 40-100GbE parameter editor, the IP core requires additional resources to implement the additional
functionality.
UG-01172
2015.05.04
Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores
1-7
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Altera Corporation
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