Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuel d'utilisateur Page 148
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- Table des matières
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Noté. / 5. Basé sur avis des utilisateurs
Address Name- Description Access
0x946
CNTR_RX_STATUS • Bit [1]: Indicates that the RX statistics registers are
paused (while CNTR_RX_CONFIG[2] is asserted) .
• Bit [0]: Indicates the presence of at least one parity
error in the RX statistics counters.
Bits [31:2] are Reserved.
RO
0x960 RxOctetsOK_LO Number of received payload bytes in frames with no FCS,
undersized, oversized, or payload length errors. This
register is compliant with section 5.2.1.14 of the IEEE
Standard 802.3-2008.
Instead of an increment vector, this register corresponds to
the signals rx_inc_octetsOK[15:0] and rx_inc_
octetsOK_valid.
RO
0x961 RxOctetsOK_HI RO
Related Information
Statistics Counters Interface on page 3-34
1588 PTP Registers
The 1588 PTP registers together with the 1588 PTP signals process and provide Precision Time Protocol
(PTP) timestamp information as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol
for Networked Measurement and Control Systems Standard. The 1588 PTP module provides you the
support to implement the 1588 Precision Time Protocol in your design.
Table 3-30: TX 1588 PTP Registers
Addr Name Bit Description HW Reset
Value
Access
0xA00 TXPTP_REVID [31:0] IP core revision ID. RO
0xA01 TXPTP_
SCRATCH
[31:0] Scratch register available for testing. 32'b0 RW
0xA02 TXPTP_NAME_
0
[31:0] First 4 characters of IP core variation
identifier string "40gPTPTxCSR" or
"100gPTPTxCSR"
RO
0xA03 TXPTP_NAME_
1
[31:0] Next 4 characters of IP core variation
identifier string "40gPTPTxCSR" or
"100gPTPTxCSR"
RO
0xA04 TXPTP_NAME_
2
[31:0] Final 4 characters of IP core variation
identifier string "40gPTPTxCSR" or
"100gPTPTxCSR"
RO
UG-01172
2015.05.04
1588 PTP Registers
3-103
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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