Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuel d'utilisateur Page 111
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Noté. / 5. Basé sur avis des utilisateurs
Word Offset Register Description
0x50A Enable RX payload length checking register
Provides enable bit to determine whether the RX error signal flags payload lengths that do
not match the length field..
0x605–
0x60A
Transmit side pause registers
Accessible only if you set Flow control mode to the value Standard flow control or
Priority-based flow control.
0x700–
0x703
Receive side pause registers
Accessible only if you set Flow control mode to the value Standard flow control or
Priority-based flow control.
0x800–
0x837
Transmit side statistics registers
Accessible only if you turn on Enable TX statistics
0x845
Transmit statistics counters configuration register CNTR_TX_CONFIG
Accessible only if you turn on Enable TX statistics
0x846
Transmit statistics counters status register
Accessible only if you turn on Enable TX statistics
0x900–
0x937
Receive side statistics registers
Accessible only if you turn on Enable RX statistics
0x945
Receive statistics counters configuration register CNTR_RX_CONFIG
Accessible only if you turn on Enable RX statistics
0x946
Receive statistics counters status register
Accessible only if you turn on Enable RX statistics
0xA00–
0xA0A
TX 1588 PTP registers
Accessible only if you turn on Enable 1588 PTP
0xB00–
0xB05
RX 1588 PTP registers
Accessible only if you turn on Enable 1588 PTP
Related Information
• Control and Status Interface on page 3-49
• PHY Registers on page 3-67
• Link Fault Signaling Registers on page 3-70
Describes the fault link signaling and fault status signal registers.
• Low Latency 40-100GbE IP Core MAC Configuration Registers on page 3-83
3-66
Software Interface: Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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