Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuel d'utilisateur Page 178
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Word Addr Bit R/W Name Description
0x4D4
29:24
RO LP coefficient
status[5:0]
Status report register reflects the contents of the
second, 16-bit word of the training frame most
recently received from the control channel: The
following fields are defined:
• [5:4]: Coefficient (+1)
• 2'b11: Maximum
• 2'b01: Minimum
• 2'b10: Updated
• 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• n [1:0]: Coefficient (-1) (same encoding as
[5:4])
For more information, refer to 10G BASE-KR LP
status report register bits (1.153.5:0) in Clause
45.2.1.79 of IEEE 802.3ap-2007.
30
RO LP Receiver ready When set to 1, the link partner receiver has
determined that training is complete and is
prepared to receive data. When set to 0, the link
partner receiver is requesting that training
continue.
Values for the receiver ready bit are defined in
Clause 72.6.10.2.4.4. For more information, refer to
10G BASE-KR LP status report register bits
(1.153.15) in Clause 45.2.1.79 of IEEE 802.3ap-
2007.
0x4D5
4:0 R LT V
OD
setting Stores the most recent TX V
OD
setting trained by
the link partner's RX based on the LT coefficient
update logic driven by Clause 72. It reflects Link
Partner commands to fine-tune the TX
preemphasis taps.
13:8 R LT Post-tap setting Stores the most recent TX post-tap setting trained
by the link partner’s RX based on the LT coefficient
update logic driven by Clause 72. It reflects Link
Partner commands to fine-tune the TX
pre-emphasis taps.
20:16 R LT Pre-tap setting Store the most recent TX pre-tap setting trained by
the link partner’s RX based on the LT coefficient
update logic driven by Clause 72. It reflects Link
Partner commands to fine-tune the TX
pre-emphasis taps.
UG-01172
2015.05.04
10GBASE-KR PHY Register Definitions
B-19
Arria 10 10GBASE-KR Registers
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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