Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuel d'utilisateur Page 95
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Signal Name Direction Description
tap_to_upd[11:0]
Output Specifies the TX equalization tap to update to optimize
signal quality. Each lane's field has the following valid
values:
• 3'b100: main tap
• 3'b010: post-tap
• 3'b001: pre-tap
This signal is present only if link training is enabled.
seq_start_rc[3:0]
Output When a bit is asserted, starts PCS reconfiguration for the
corresponding lane.
dfe_start_rc[3:0]
Output When a bit is asserted, starts RX DFE equalization for the
corresponding lane. This signal is present only if RX
equalization is enabled.
dfe_mode[7:0]
Output Specifies the DFE operation mode. Valid at the rising edge
of the def_start_rc signal and held until the falling edge of
the rc_busy signal. The following encodings are defined for
each lane:
• 2'b00: Disable DFE
• 2'b01: DFE triggered mode (single shot)
• 2b10 and 2'b11 are reserved.
This signal is present only if RX equalization is enabled.
ctle_start_rc[3:0]
Output When a bit is asserted, starts continuous time-linear
equalization (CTLE) reconfiguration on the corresponding
lane. This signal is present only if RX equalization is
enabled.
ctle_rc[15:0]
Output RX CTLE value. This signal is valid at the rising edge of the
ctle_start_rc signal and held until the falling edge of the
rc_busy signal. The valid range of values is 4'b0000–
4'b1111. 4'b0000 indicates the RX CTLE is disabled and
4'b1111 indicates RX CTLE is at its maximum value. This
signal is present only if RX equalization is enabled.
ctle_mode[7:0]
Output Specifies the CTLE mode. This signal is valid at the rising
edge of the ctle_start_rc signal and held until the falling
edge of the rc_busy signal. The only valid value of this
signal in the 40-100GbE IP core is 2'b0. This signal is
present only if RX equalization is enabled.
3-48
40GBASE-KR4 Reconfiguration Interface
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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