Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuel d'utilisateur Page 86
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Signal Name Direction Description
local_fault_status
Output
Asserted when local fault is detected in RX MAC in a duplex IP
core variation. In duplex IP core variations, local_fault_from_
rx is connected internally to local_fault_to_tx, and this signal
is available externally as local_fault_status.
Related Information
• Link Fault Signaling Registers on page 3-88
Information about the Enable Link Fault Sequence register and the MAC/RS link fault
sequence configuration register.
• IEEE website
The IEEE 802.3ba –2010 100G Ethernet Standard is available on the IEEE website.
Statistics Counters Interface
The statistics counters module is a synthesis option that you select in the 40-100GbE parameter editor.
However, the statistics status bit output vectors are provided whether you select the statistics counters
module option or not.
The increment vectors are brought to the top level as output ports. If you configure the statistics counters
module, the increment vectors also function as input ports to the control and status registers (CSR).
Table 3-9: Statistics Counters Increment Vectors
The TX statistics counter increment vectors are clocked by the clk_txmac clock, and the RX statistics counter
increment vectors are clocked by the clk_rxmac clock.
Name Signal
Direction
Description
TX Statistics Counter Increment Vectors
tx_inc_64
Output Asserted for one cycle when a 64-byte TX frame is transmitted.
tx_inc_127
Output Asserted for one cycle when a 65–127 byte TX frame is transmitted.
tx_inc_255
Output Asserted for one cycle when a 128–255 byte TX frame is transmitted.
tx_inc_511
Output Asserted for one cycle when a 256–511 byte TX frame is transmitted.
tx_inc_1023
Output Asserted for one cycle when a 512–1023 byte TX frame is transmitted.
tx_inc_1518
Output Asserted for one cycle when a 1024–1518 byte TX frame is transmitted.
tx_inc_max
Output Asserted for one cycle when a maximum-size TX frame is transmitted.
tx_inc_over
Output Asserted for one cycle when an oversized TX frame is transmitted.
UG-01088
2014.12.15
Statistics Counters Interface
3-39
Functional Description
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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