Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuel d'utilisateur Page 193
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Date ACDS
Version
Changes
June 2013 1.3(v13.0
software
release)
• Updated for use with version 13.0 of the Quartus II software and the
MegaWizard Plug-In Manager.
• Added preamble pass-through option. This change affects various
sections in “TX Datapath” on page 3–5 and “RX Datapath” on page 3–
20, and includes the addition of a new Preamble Pass-Through
Configuration register (offset 0x125), described in “MAC Feature
Configuration Registers” on page 3–62.
• Added transmitter average inter-packet gap (IPG) adjustment option.
This change affects “Inter-Packet Gap Generation and Insertion” on
page 3–7 and includes the addition of two new registers (IPG_DEL_
PERIOD at offset 0x126 and IPG_DEL_ENABLE at offset 0x127), described
in “R**MAC Feature Configuration Registers” on page 3–62.
• Added new section “MAC Feature Configuration Registers” on page 3–
62 for the new registers. Moved the description of the CRC_CONFIG
register (offset 0x123) to this new section.
• Reorganized Chapter 2, Getting Started to remove non-IP core specific
information.
• Moved instructions for IP core initialization from “Software Interface:
Registers” to new section “Initializing the IP Core” on page 2–30.
• Updated resource utilization numbers in “Performance and Resource
Utilization” on page 1–5.
• Clarified device speed grades per device family variant, in “Device Speed
Grade Support” on page 1–4.
• Clarified definitions of cut-through, store and forward, and
promiscuous receive modes, in “40-100GbE IP Core Modes of
Operation” on page 3–34.
• Clarified destination address checking controls in “Address Checking ”
on page 3–22 and in “MAC Address Registers” on page 3–64.
• Removed Appendix B, Address Map Changes for 12.1, and moved
information to Document Revision History entry for Quartus II
software v12.1 release. The update added registers but did not change
register names or offsets of existing registers.
• Fixed descriptions of allowed transceiver reference clock frequencies
and PCS clock frequencies:
• Clarified that 644 MHz is not an allowed frequency for CAUI–4
variations, despite its presence in the parameter editor as an
apparently allowed value for the PHY Reference Frequency
parameter.
• Provided correct PCS clock frequency for CAUI–4 variations.
• Provided correct frequencies for 24.24 Gbps variations.
• Modified “100GbE IP Core without Adapters” on page 3–14 to clarify
that only two SOPs can occur on the TX custom streaming client
interface during the same clock cycle.
• Added instructions for using the example design in Appendix A, 13.0
Example Design.
• Improved descriptions of various signals and fixed typos.
D-4
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
UG-01088
2014.12.15
Altera Corporation
Additional Information
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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