Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuel d'utilisateur Page 83
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Signal Name Direction Description
pause_insert_mcast Input When asserted, specifies that the IP core should generate a pause
packet with the well-known multicast address of 01-80-C2-00-00-
01. If deasserted, the pause is generated with the specified MAC
address (pause_insert_dst), which is typically a unicast address.
pause_insert_dst
[47:0]
Input Specifies the MAC address for a unicast pause.
pause_insert_src
[47:0]
Input Specifies source address of the pause packet.
pause_match_from_rx
Output Asserted to indicate an RX pause signal match. Used only when
RX configurations are instantiated. The IP core asserts this signal
when it receives a pause request with an address match, to signal
the TX MAC to throttle its transmissions on the Ethernet link.
pause_time_from_
rx[15:0]
Output Asserted for RX pause time. Used only when RX configurations
are instantiated.
pause_match_to_tx
Input Asserted to indicate a TX pause signal match. Used only when TX
configurations are instantiated.
pause_time_to_
tx[15:0]
Input Asserted for TX pause time. Used only when TX configurations
are instantiated.
Related Information
• Pause Control Frame and Non-Pause Control Frame Filtering and Forwarding on page 3-36
Information about enabling and disabling the pause packets pass-through.
• Pause Registers on page 3-102
You can access the pause functionality using the pause registers for any 40-100GbE IP core variation
that includes a MAC component. Values you program in the registers specify the pause quanta.
Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding
The 40GbE and 100GbE MAC IP cores can pass the pause packets through as normal traffic or drop the
pause control frames in the RX direction. You can enable and disable pass-through with the following
configuration control bits:
• RX_FILTER_CTRL bit [4] enables and disables pause filtering.
• RX_FILTER_CTRL bit [5] enables and disables control filtering.
By default, pass-through is disabled.
The following rules define pause control frames filtering control:
1. The RX_FILTER_CTRL register contains options to filter different packets types, such as runt packets,
FCS error packets, address mismatch packets, and so on, from the RX MAC. The RX_FILTER_CTRL
register contains one bit to enable pause packet filtering and one bit to enable non-pause control
3-36
Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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