Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuel d'utilisateur Page 176
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Word
Addr
Bit R/W Name Description
18 RW Assert KR FEC
Request
When set to 1, indicates that the core is requesting the FEC
ability. When this bit changes, you must assert the Reset SEQ
bit (0xB0[0]) to renegotiate with the new value.
0xB1
0
R SEQ Link Ready When asserted, the sequencer is indicating that the link is
ready.
1 R SEQ AN timeout When asserted, the sequencer has had an Auto-Negotiation
timeout. This bit is latched and is reset when the sequencer
restarts Auto-Negotiation.
2 R SEQ LT timeout When set, indicates that the Sequencer has had a timeout.
13:8 R SEQ Reconfig
Mode[5:0]
Specifies the Sequencer mode for PCS reconfiguration. The
following modes are defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 10G data mode
• Bit 11, mode[3]: Gige data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit13, mode[5]: 10G FEC mode
16 R KR FEC Ability Indicates whether or not the 10GBASE-KR PHY supports
FEC. For more information, refer to the FEC variable FEC_
Enable as defined in Clause 74.8.2 and 10GBASE-KR PMD
control register bit (1.171.0) IEEE 802.3ap-2007.
17 R Enable KR FEC
Error Indication
Ability
When set to 1, indicates that the 10GBASE-KR PHY is
capable of reporting FEC decoding errors to the PCS. For
more information, refer to the KR FEC variable FEC_enable_
Error_to_PCS and 10GBASE-KR PMD control register bit
(1.171.1) as defined in Clause 74.8.3 of IEEE 302.3ap-2007.
0xB2
0 RW FEC TX trans
error
When asserted, indicates that the error insertion feature in
the FEC Transcoder is enabled.
1 RW FEC TX burst
error
When asserted, indicates that the error insertion feature in
the FEC Encoder is enabled.
5:2 RW FEC TX burst
length
Specifies the length of the error burst. Values 1-16 are
available.
10:6 Reserved
11 RWS
C
FEC TX Error
Insert
Writing a 1 inserts 1 error pulse into the TX FEC depending
on the Transcoder and Burst error settings. Software clears
this register.
31:15 RWS
C
Reserved
0xB3 31:0 RSC FEC Corrected
Blocks
Counts the number of corrected FEC blocks. Resets to 0
when read. Otherwise, it holds at the maximum count and
does not roll over. Refer to Clause 74.8.4.1 of IEEE 802.3ap-
2000 for details.
UG-01088
2014.12.15
10GBASE-KR PHY Register Definitions
C-3
10GBASE-KR Registers
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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