Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manuel d'utilisateur Page 34
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You can use the IP Catalog to generate an Altera transceiver reconfiguration controller.
• For Arria V GZ and Stratix V devices, select the Transceiver Reconfiguration Controller.
• For Stratix IV devices, select the ALTGX_RECONFIG transceiver reconfiguration block.
When you configure the Altera Transceiver Reconfiguration Controller, you must specify the number of
reconfiguration interfaces. The number of reconfiguration interfaces required for the 40GbE and 100GbE
IP cores depends on the IP core variation.
Table 2-4: Number of Reconfiguration Interfaces
Lists the number of reconfiguration interfaces you should specify for the Altera Transceiver Reconfiguration
Controller for your Arria V GZ or Stratix V 40-100GbE IP core that includes a PHY component.
PHY Configuration RX Only TX Only Duplex
Standard 40GbE and
40GBASE-KR4
(4x10.3125 lanes)
4 8 8
100GbE (10x10.3125
lanes)
10 20 20
CAUI-4 (4x25.78125
lanes)
— — 4x3
(9)
You can configure your reconfiguration controller with additional interfaces if your design connects with
multiple transceiver IP cores. You can leave other options at the default settings or modify them for your
preference.
You should connect the reconfig_to_xcvr and reconfig_from_xcvr ports of the 40-100GbE IP core to
the corresponding ports of the reconfiguration controller.
The CAUI–4 variations have four reconfiguration channels, numbered consecutively from
reconfig_to_xcvr0 and reconfig_from_xcvr0 to reconfig_to_xcvr3 and reconfig_from_xcvr3.
The CAUI–4 reconfiguration channels must be connected to the four reconfiguration controller
groupings. The reconfiguration controller groupings include ch0_2_from_xcvr, ch3_5_from_xcvr,
ch6_8_from_xcvr, and ch9_11_from_xcvr.
You must also connect the mgmt_clk_clk and mgmt_rst_reset ports of the Altera Transceiver Reconfi‐
guration Controller. The mgmt_clk_clk port must have a clock setting in the range of 100–125MHz; this
setting can be shared with the 40-100GbE IP core clk_status port. The mgmt_rst_reset port must be
deasserted before, or deasserted simultaneously with, the 40-100GbE IP core pma_arst_ST port.
(9)
The CAUI-4 configuration requires 12 interfaces split into four groups of three; the interface grouping
should be set to 3, 3, 3, 3.
2-12
External Transceiver Reconfiguration Controller
UG-01088
2014.12.15
Altera Corporation
Getting Started
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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