Altera Stratix V Avalon-ST Manuel d'utilisateur Page 98
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Noté. / 5. Basé sur avis des utilisateurs
Lane Error Status Register
Table 5-39: Lane Error Status Register - 0x208
Bits Register Description Default Value Access
[7:0] Lane Error Status: Each 1 indicates an error was detected in the
corresponding lane. Only Bit 0 is implemented when the link
width is 1. Bits [1:0] are implemented when the link width is 2,
and so on. The other bits read as 0. This register is present only in
PF0 when the maximum data rate is 8 Gbps.
0 RW1CS
[31:8] Reserved 0 RO
Table 5-40: Lane Equalization Control Registers 0–3: 0x20C–0x218
This register contains the Transmitter Preset and the Receiver Preset Hint values. The Training Sequences capture
these values during Link Equalization. This register is present only in PF0 when the maximum data rate is 8 Gbps.
Lane Equalization Control Registers 0 at address 0x20C records values for lanes 0 and 1. Lane Equalization
Control Registers 0 at address 0x20C records values for lanes 2 and 3, and so on.
Bits Register Description Default Value Accress
[6:0] Reserved 0x7F RO
[7] Reserved 0 RO
[11:8] Upstream Port Lane 0 Transmitter Preset 0xF RO
[14:12] Upstream Port Lane 0 Receiver Preset Hint 0x7 RO
[15] Reserved 0 RO
[22:16] Reserved 0x7F RO
[23] Reserved 0 RO
[27:24] Upstream Port Lane 1 Transmitter Preset 0xF when link
width > 1
0 when link
width = 1
RO
[30:28] Upstream Port Lane 1 Receiver Preset Hint 0x7 when link
width > 1
0 when link
width = 1
RO
5-24
Lane Error Status Register
UG-01097_sriov
2014.12.15
Altera Corporation
Registers
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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