Altera Stratix V Avalon-ST Manuel d'utilisateur télécharger pdf (Page 140)

As this figure illustrates, the reconfig_to_xcvr[ <n> 70-1:0] and reconfig_from_xcvr[ <n> 46-1:0]

buses connect the two components. You must provide a 100–125 MHz free-running clock to the

mgmt_clk_clk clock input of the Transceiver Reconfiguration Controller IP Core.

Initially, each lane and TX PLL require a separate reconfiguration interface. The parameter editor reports

this number in the message pane. You must take note of this number so that you can enter it as a

parameter value in the Transceiver Reconfiguration Controller parameter editor. The following figure

illustrates the messages reported for a Gen2 ×4 variant. The variant requires five interfaces: one for each

lane and one for the TX PLL.

Figure 11-2: Number of External Reconfiguration Controller Interfaces

When you instantiate the Transceiver Reconfiguration Controller, you must specify the required Number

of reconfiguration interfaces as the following figure illustrates.

11-2

Connecting the Transceiver Reconfiguration Controller IP Core

UG-01097_sriov

2014.12.15

Altera Corporation

Transceiver PHY IP Reconfiguration

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Altera Stratix V Avalon-ST Manuel d'utilisateur Page 140