Altera Stratix V Avalon-ST Manuel d'utilisateur Page 127
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Interrupts
The Hard IP for PCI Express offers the following interrupt mechanisms:
• Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge
handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configu‐
ration Space and is programmable using Configuration Space accesses. MSI interrupts are only
supported for Physical Functions.
• MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. In
contrast to the MSI capability structure, which contains all of the control and status information for
the interrupt vectors, the MSI-X Capability structure points to an MSI-X table structure and MSI-X
PBA structure which are stored in memory. MSI-X interrupts are supported for Physical and Virtual
Functions.
• Legacy interrupts—The app_int_sts port controls legacy interrupt generation. When app_int_sts is
asserted, the Hard IP generates an Assert_INT<n> message TLP.
• MSI interrupts are only supported for Physical Functions.
PIPE
The PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallel
interface to speed simulation; however, you cannot use the PIPE interface in actual hardware.
• The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation.
• For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants
can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
Related Information
PIPE Interface Signals on page 4-36
Data Link Layer
The Data Link Layer is located between the Transaction Layer and the Physical Layer. It maintains packet
integrity and communicates (by DLL packet transmission) at the PCI Express link level (as opposed to
component communication by TLP transmission in the interconnect fabric).
The DLL implements the following functions:
• Link management through the reception and transmission of DLL packets (DLLP), which are used for
the following functions:
• Power management of DLLP reception and transmission
• To transmit and receive ACK/NACK packets
• Data integrity through generation and checking of CRCs for TLPs and DLLPs
• TLP retransmission in case of NAK DLLP reception using the retry buffer
• Management of the retry buffer
• Link retraining requests in case of error through the Link Training and Status State Machine
(LTSSM) of the Physical Layer
UG-01097_sriov
2014.12.15
Interrupts
9-3
IP Core Architecture
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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