Altera Stratix V Avalon-ST Manuel d'utilisateur Page 36
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Interfaces and Signal Descriptions
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tx_out0[<n>-1:0]
rx_in0[<n>-1:0]
Hard IP Serial
Hard IP Reset
Status
Hard IP for PCI Express with SR-IOV
flr_active_pf[<n>-1:0]
flr_active_vf[<n>-1:0]
flr_completed_pf[<n>-1:0]
refclk
coreclkout
pld_clk
flr_completed_vf[<n>-1:0]
cpl_err[6:0]
cpl_err_fn[7:0]
cpl_pending_pf[<n>-1:0]
cpl_pending_vf[<n>-1:0]
log_hdr[127:0]
tx_st_data[<n>-1:0]
tx_st_sop
tx_st_eop
tx_st_ready
tx_st_valid
tx_st_empty[1:0]
tx_st_err
bus_master_en_vf[<n>-1:0]
bus_master_en_pf[<n>-1:0]
bus_num_f0[7:0]
bus_num_f1[7:0]
device_num_f0[4:0]
device_num_f1[4:0]
max_payload_size[2:0]
mem_space_en_pf[<n>-1:0]
mem_space_en_vf[<n>-1:0]
pf0_num_vfs[7:0]
pf1_num_vfs[7:0]
rd_req_size[2:0]
Configuration
Status
TX Avalon-ST
TX Port
Component
Specific
TX Credit
RX Port
npor
pin_perst
Reset
Clocks
rx_st_data[<n>-1:0]
rx_st_sop
rx_st_eop
rx_st_ready
rx_st_valid
rx_st_empty[1:0]
rx_st_err
RX Avalon-ST
Component
Specific
RX BAR
Hit
rx_st_bar_hit_fn_tlp0[7:0]
rx_st_bar_hit_fn_tlp1[7:0]
rx_st_bar_hit_tlp0[7:0]
rx_st_bar_hit_tlp1[7:0]
rx_st_mask
tx_cred_datafccp[11:0]
tx_cred_datafcnp[11:0]
tx_cred_datafcp[11:0]
tx_cred_fchipcons[5:0]
tx_cred_fc_infinite[5:0]
tx_cred_hdrfccp[7:0]
tx_cred_hdrfcnp[7:0]
tx_cred_hdrfcp[7:0]
Function Level
Reset
Completion
Error Status
and Pending
Hard IP Control,
Miscellaneous &
Current Speed
test_in[31:0]
simu_mode_pipe
current_speed[1:0]
hpg_ctrler[4:0]
pld_clk_inuse
pld_core_ready
reset_status
serdes_pll_locked
testin_zero
reconfig_from_xcvr[<n>46-1:0]
reconfig_to_xcvr[<n>70-1:0]
Transceiver
Reconfiguration
LMI
lmi_dout[31:0]
lmi_func[8:0]
lmi_rden
lmi_wren
lmi_ack
app_int_sts_a
app_int_sts_b
app_int_sts_c
app_int_sts_d
app_int_ack
app_int_pend_status[1:0]
app_int_sts_fn
app_intx_disable[1:0]
lmi_addr[11:0]
lmi_din[31:0]
MSI
Interrupts
Select One
Interrupt
Mechanism
MSI-X
Interrupts
Legacy
Interrupts
app_msi_req
app_msi_req_fn[7:0]
app_msi_ack
app_msi_addr[127:0]
app_msi_data_pf[16<n>-1:0]
app_msi_enable_pf[1:0]
app_msi_mask_pf[32<n>-1:0]
app_msi_multi_msg_enable_pf[5:0]
app_msi_num[4:0]
app_msi_pending_bit_write_data
app_msi_pending_bit_write_en
app_msi_pending_pf[63:0]
app_msi_tc[2:0]
app_msi_status[1:0]
app_msix_req
app_msix_ack
app_msix_addr_pf[63:0]
app_msix_data[31:0]
app_msix_en_pf[1:0]
app_msix_en_vf[<n>-1:0]
app_msix_err
app_msix_fn_mask_pf[1:0]
app_msix_fn_mask_vf[<n>-1:0]
ko_clp_spc_data[11:0]
ko_cpl_spc_header[7:0]
nik1410905520092.image
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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ISO
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Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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