Altera Stratix V Avalon-ST Manuel d'utilisateur Page 44
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Signal Direction Description
rx_st_mask Input
The Application Layer asserts this signal to tell the Hard IP to
stop sending non-posted requests. This signal can be asserted at
any time. Up to 10 non-posted requests can be transferred to the
Application Layer after rx_st_mask is asserted.
Configuration Status Interface
The output signals listed below drive the settings of the various configuration register fields of the
Functions. These settings are often needed in designing Application Layer logic.
Table 4-4: Configuration Status Interface
Signal Direction Description
bus_num_f0[7:0] Output
Direction
Bus number assigned to Physical Function 0 by the Root
Complex, as captured from CfgWr transactions.
When ARI is enabled, the Application Layer must use this bus
number for all TLP requests and completions. When ARI is not
enabled, the Application Layer must use this bus number for TLP
requests and completions from PF0 and its associated Virtual
Functions.
bus_num_f1[7:0] Output Bus number assigned to Physical Function 1 by the Root
Complex, as captured from CfgWr transactions.
When ARI is enabled,bus_num_f1 is not used. When ARI is not
enabled, the application layer must use this bus number for TLP
requests and completions from PF1 and its associated Virtual
Functions.
device_num_f0[4:0] Output Device number assigned to Physical Function 0 by the Root
Complex, as captured from CfgWr transactions.
When ARI is enabled, the Requester ID only consists of bus
number and function number. Consequently, device_num_f0 is
unused. When ARI is disabled, the Application Layer must use
device_num_f0 for all TLP requests and completions from PF0
and its associated VFs.
device_num_f1[4:0] Output Device number assigned to Physical Function 1 by the Root
Complex, as captured from CfgWr transactions.
When ARI is enabled, the Requester ID only consists of bus
number and function number. Consequently, device_num_f1 is
unused. When ARI is disabled, the Application Layer must use
device_num_f1 for all TLP requests and completions from PF0
and its associated VFs.
UG-01097_sriov
2014.12.15
Configuration Status Interface
4-9
Interfaces and Signal Descriptions
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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